Postgraduate Diploma in MCU/NPU Inference (TFLite/ONNX/TensorRT)
Online 800 h Postgraduate Diploma in MCU/NPU inference (TFLite/ONNX/TensorRT). 8 modules covering ISO/PAS 8800 (artificial intelligence in road vehicles), ISO 26262 (functional safety in automotive) and TensorFlow Lite / LiteRT. Assigned tutor and open enrolment.
Take the controls.
Run a real engineering trade-off from this field. Move the sliders, watch the model react in real time and beat the challenge.
What you will be able to do
Compare MCU, NPU and embedded GPU architectures for inference.
Design efficient models for limited resources.
Apply quantisation techniques and assess their impact on accuracy.
Deploy models with TensorFlow Lite on microcontrollers.
Export and run models with ONNX Runtime.
Optimise inference on embedded GPUs with TensorRT.
Put embedded inference systems into production and monitor them.
Who it's for
- Embedded machine learning engineer who wants to specialise in Inference in MCU/NPUs (TFLite/ONNX/TensorRT).
- Embedded software engineer who wants to specialise in Inference in MCU/NPUs (TFLite/ONNX/TensorRT).
- Edge MLOps engineer who wants to specialise in Inference in MCU/NPUs (TFLite/ONNX/TensorRT).
- Embedded computer vision developer who wants to specialise in Inference in MCU/NPUs (TFLite/ONNX/TensorRT).
- AI hardware architect who wants to specialise in Inference in MCU/NPUs (TFLite/ONNX/TensorRT).
- Model optimisation engineer who wants to specialise in Inference in MCU/NPUs (TFLite/ONNX/TensorRT).
- Graduates in engineering or sciences seeking to enter consumer electronics.
What you'll work with
- ISO/PAS 8800 (artificial intelligence in road vehicles)
- ISO 26262 (functional safety in automotive)
- IEC 61508
- ONNX specification
- MISRA C:2012
- ISO/IEC 22989 (AI concepts)
- Regulation (EU) 2024/1689 (AI Act)
8 modules · 800 h
1.1Cortex-M and RISC-V microcontrollers1.2DSP extensions and Helium (MVE)1.3Embedded NPUs: Ethos-U and similar1.4SoCs with accelerators: Jetson and Coral1.5Memory hierarchy: SRAM, flash and DRAM1.6Energy consumption and power budgets1.7Metrics: latency, throughput and TOPS/W1.8MLPerf Tiny benchmarks1.9Platform selection by application1.10Case study: comparing platforms for keyword spotting
2.1Lightweight architectures: MobileNet and EfficientNet2.2Networks for time series and audio2.3Depthwise separable convolutions2.4Architecture search for MCUs: MCUNet2.5Knowledge distillation2.6Structured and unstructured pruning2.7Low-rank factorisation2.8Calculating MACs and activation memory2.9The accuracy-efficiency trade-off2.10Practice: training a compact model in Keras
3.1Fixed-point and integer representation3.2Post-training quantisation3.3Quantisation-aware training3.4Per-tensor and per-channel quantisation3.5Calibration with representative data3.6INT8, INT4 and mixed precision3.7Effects on accuracy and debugging3.8Quantisation of activations and biases3.9Compressed weight formats3.10Lab: INT8 quantisation with TFLite Converter
4.1FlatBuffer conversion workflow4.2TFLite Micro interpreter4.3Operator resolution and registration4.4Tensor arena and memory planning4.5Optimised CMSIS-NN kernels4.6Delegates for NPUs4.7Deployment on STM32 and nRF boards4.8Per-layer latency profiling4.9On-device debugging4.10Lab: deploying a classifier on Cortex-M4
5.1ONNX format: graph, operators and opsets5.2Exporting from PyTorch5.3Graph optimisation and operator fusion5.4ONNX Runtime and execution providers5.5Quantisation in ONNX Runtime5.6Tools: Netron and onnx-simplifier5.7Compilers: TVM and microTVM5.8Interoperability between frameworks5.9Numerical validation after conversion5.10Practice: exporting and optimising a PyTorch model
6.1TensorRT architecture6.2Building engines and optimisation profiles6.3FP16 and INT8 precision with calibration6.4Custom layers and plugins6.5DLA on Jetson platforms6.6DeepStream for video6.7Memory management and CUDA streams6.8Profiling with Nsight Systems6.9Container deployment6.10Lab: accelerating a detector with TensorRT on Jetson
7.1On-device sensor pre-processing7.2Audio, video and IMU pipelines7.3OTA model updates7.4Model security and encryption7.5Drift monitoring at the edge7.6Federated and on-device learning7.7Real-time requirements and RTOS7.8Firmware testing and validation7.9MLOps for embedded systems7.10Case study: predictive maintenance with vibration on MCU
8.1Defining the use case8.2Hardware selection8.3Data collection and preparation8.4Model design and training8.5Optimisation and quantisation8.6Deployment and profiling8.7Field validation8.8Power consumption and cost analysis8.9Report and presentation8.10Final review with the tutor
How you'll learn
Fully 100% online training on the SEIUM campus, with downloadable material, recorded classes and an assigned technical tutor. No fixed timetables: students progress at their own pace within the enrolment period, which makes it possible to combine study with work.
Each module combines theory, guided reading of the original standard and applied exercises. The working software is TensorFlow Lite / LiteRT, ONNX Runtime, NVIDIA TensorRT, STM32Cube.AI, Edge Impulse, in free, academic or evaluation versions. Tests are studied using real benchmarking procedures for latency and power consumption (MLPerf Tiny), microcontroller deployment, and accuracy comparisons after quantisation. Assessment is continuous per module plus the final integrating project.
Build it end to end
Your final project follows the real engineering workflow, step by step, reviewed by your tutor.
Compare MCU, NPU and embedded GPU architectures for inference.
Design efficient models for limited resources.
Apply quantisation techniques and assess their impact on accuracy.
Deploy models with TensorFlow Lite on microcontrollers.
Export and run models with ONNX Runtime.
Where this takes you
Requirements
- Prior technical training or professional experience in the sector. A university degree is not required.
- Internet connection and a computer capable of running the programme's software.
- Sufficient level of Spanish to follow technical regulatory texts.
Ready to start?
Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.
Frequently asked questions
The programme comprises 800 total hours spread over 6 to 8 months. That is an average of 10 to 15 hours per week, compatible with a full-time job.
The programme works with TensorFlow Lite / LiteRT, ONNX Runtime, NVIDIA TensorRT, STM32Cube.AI, Edge Impulse. Free, academic or evaluation versions are used, and the tutor indicates the free alternative where one exists.
A SEIUM own diploma upon passing the continuous assessment and the integrating project. It is in-house training, not an official title from the Ministry.
Yes. Modules passed in a course or postgraduate diploma in the same area are recognised in the advanced programme. Check the recognition policy when you enrol.
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