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Master'sElectronics, Embedded Systems & Telecom Applications open

Master’s in Real-Time Scheduling and Timing Analysis Engineering

Online master's programme of 1,900 hours in real-time scheduling engineering and timing analysis. 12 modules covering fixed- and dynamic-priority scheduling, WCET analysis, multicore and distributed timing, ARINC 653 partitioning and timing evidence for certification under IEC 61508-3, ISO 26262-6 and DO-178C, with an assigned technical tutor.

Duration1900 h
ModeOnline
LanguageEnglish
Start datesSet by the faculty
AwardSEIUM Institute diploma
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Learning outcomes

What you will be able to do

01

Model real-time systems with their timing constraints.

02

Apply fixed- and dynamic-priority scheduling algorithms.

03

Calculate response times and verify schedulability.

04

Estimate worst-case execution time using static and hybrid techniques.

05

Analyse timing in multicore and distributed systems.

06

Design partitioned systems with temporal isolation.

07

Produce timing evidence for certification processes.

Profile

Who it's for

  • Real-time systems engineers looking to deepen their scheduling and timing analysis expertise.
  • Timing analysts working on safety-critical software.
  • Critical software engineers in aerospace, automotive or rail.
  • Embedded software architects responsible for multitasking and multicore designs.
  • Functional safety engineers who need to assess timing behaviour.
  • Timing verification engineers preparing certification evidence.
  • Engineering or science graduates seeking to move into the aerospace sector.
Standards & tools

What you'll work with

  • IEC 61508-3 (software requirements for functional safety)
  • ISO 26262-6 (product development at the software level)
  • RTCA DO-178C (software considerations in airborne systems)
  • ARINC 653 (avionics application software standard interface)
  • CAST-32A (multi-core processors)
  • AMC 20-193 (use of multi-core processors)
  • IEEE 1003.1 POSIX Realtime Extensions (real-time operating system interface)
  • ECSS-E-ST-40C (space software engineering)
  • MAST
  • Cheddar
  • aiT WCET Analyzer
  • RapiTime
  • Inchron chronSUITE
Syllabus

12 modules · 1900 h

  1. 1.1Definition and classification of real-time systems
  2. 1.2Deadlines, periods and response times
  3. 1.3Hard and soft critical systems
  4. 1.4Cyclic versus multitasking architectures
  5. 1.5Periodic task model
  6. 1.6Sporadic and event-driven activations
  7. 1.7Timing failures and their consequences
  8. 1.8Examples in avionics and automotive
  9. 1.9Timing requirements and their specification
  10. 1.10Case study: timing specification of a controller
  1. 2.1Rate-monotonic priority assignment
  2. 2.2Deadline-monotonic priority assignment
  3. 2.3Liu and Layland utilisation test
  4. 2.4Exact response-time analysis
  5. 2.5Critical instant and priority level
  6. 2.6Audsley's optimal priority assignment
  7. 2.7Release jitter and its effect
  8. 2.8Scheduler overhead and context switches
  9. 2.9Non-preemptive and deferred preemption scheduling
  10. 2.10Practical: response-time analysis with MAST
  1. 3.1Earliest Deadline First (EDF) scheduling
  2. 3.2Least-laxity scheduling
  3. 3.3Processor demand analysis
  4. 3.4Comparison of EDF and fixed priorities
  5. 3.5Behaviour under overload
  6. 3.6Resource reservation scheduling
  7. 3.7Linux SCHED_DEADLINE scheduler
  8. 3.8Static cyclic scheduling
  9. 3.9Building execution tables
  10. 3.10Lab: scheduler simulation with Cheddar
  1. 4.1Unbounded priority inversion
  2. 4.2Priority inheritance protocol
  3. 4.3Priority ceiling protocol
  4. 4.4Stack resource policy
  5. 4.5Calculating blocking times
  6. 4.6Deadlocks and their prevention
  7. 4.7Synchronisation on multiprocessors
  8. 4.8MPCP and MrsP protocols
  9. 4.9Implementation in commercial RTOSs
  10. 4.10Workshop: blocking analysis of a system with mutexes
  1. 5.1The WCET concept and its bounds
  2. 5.2Static control-flow analysis
  3. 5.3Modelling caches and pipelines
  4. 5.4Measurement-based analysis
  5. 5.5Hybrid analysis with RapiTime
  6. 5.6Probabilistic WCET analysis
  7. 5.7Influence of the compiler
  8. 5.8Loop and path annotations
  9. 5.9Validating WCET bounds
  10. 5.10Practical: WCET calculation with aiT
  1. 6.1Servicing aperiodic events
  2. 6.2Deferrable server and its analysis
  3. 6.3Sporadic server and its analysis
  4. 6.4Constant bandwidth servers
  5. 6.5Handling interrupts as tasks
  6. 6.6Analysis of event handlers
  7. 6.7Overload tolerance
  8. 6.8Implementation in POSIX
  9. 6.9Scheduling mixed-mode tasks
  10. 6.10Case study: design of a sporadic server
  1. 7.1Partitioned and global scheduling
  2. 7.2Allocating tasks to cores
  3. 7.3Interference from shared resources
  4. 7.4Memory and bus contention
  5. 7.5Cache and bandwidth partitioning
  6. 7.6CAST-32A and AMC 20-193 requirements
  7. 7.7Measuring interference with microbenchmarks
  8. 7.8Interference mitigation
  9. 7.9Multicore analysis tools
  10. 7.10Lab: measuring inter-core interference
  1. 8.1Deterministic communication networks
  2. 8.2Timing analysis of the CAN bus
  3. 8.3TSN networks and traffic scheduling
  4. 8.4AFDX in avionics
  5. 8.5End-to-end analysis
  6. 8.6Holistic transaction analysis
  7. 8.7Clock synchronisation with PTP
  8. 8.8Cause-effect chains
  9. 8.9Distributed analysis tools
  10. 8.10Workshop: timing analysis of a CAN network
  1. 9.1The ARINC 653 standard
  2. 9.2Separation hypervisors
  3. 9.3Partition scheduling tables
  4. 9.4Hierarchical schedulability analysis
  5. 9.5Temporal and spatial isolation
  6. 9.6Mixed-criticality systems
  7. 9.7Partition configuration
  8. 9.8Verification of separation
  9. 9.9Cases in integrated modular avionics
  10. 9.10Practical: design of an ARINC 653 partition table
  1. 10.1Modelling with UML MARTE
  2. 10.2AUTOSAR timing extensions
  3. 10.3Analysis models with MAST
  4. 10.4Event chains and latencies
  5. 10.5Design space exploration
  6. 10.6Optimisation of priorities and periods
  7. 10.7Simulation versus formal analysis
  8. 10.8Integration into the development workflow
  9. 10.9Model validation with traces
  10. 10.10Case study: timing model of an AUTOSAR ECU
  1. 11.1Timing objectives in DO-178C
  2. 11.2ISO 26262 timing requirements
  3. 11.3IEC 61508 requirements
  4. 11.4ECSS-E-ST-40C requirements
  5. 11.5Qualification of analysis tools
  6. 11.6Stress and overload testing
  7. 11.7Timing coverage and traceability
  8. 11.8Timing analysis reports
  9. 11.9Review by the authority
  10. 11.10Workshop: timing evidence dossier
  1. 12.1Definition of the system under study
  2. 12.2Modelling tasks and resources
  3. 12.3WCET estimation
  4. 12.4Schedulability analysis
  5. 12.5Design of the timing architecture
  6. 12.6Verification by simulation and measurement
  7. 12.7Preparation of evidence
  8. 12.8Conclusions and future work
  9. 12.9Master's Thesis report
  10. 12.10Master's Thesis: defence before a panel
Methodology, software & labs

How you'll learn

Training is 100% online on the SEIUM campus, with downloadable material, recorded classes and an assigned technical tutor. There are no fixed timetables: you progress at your own pace within the intake, so it fits around your job.

Each module combines theory, guided reading of the original standard and applied exercises. The working software is MAST, Cheddar, aiT WCET Analyzer, RapiTime and Inchron chronSUITE, in free, academic or evaluation versions. Analyses are studied on real procedures: response-time analysis of a multitasking system, worst-case execution time estimation and interference analysis on multicore processors. Assessment is continuous per module, plus the final Master's Thesis.

Standards covered: IEC 61508-3, ISO 26262-6, RTCA DO-178C, ARINC 653, CAST-32A, AMC 20-193, IEEE 1003.1 POSIX Realtime Extensions, ECSS-E-ST-40C.

Assigned technical tutor:every module ends with a deliverable that your tutor marks individually.
Standards-based learning:guided reading of IEC 61508-3, ISO 26262-6 and DO-178C applied to real cases, not as a theoretical annex.
Industry software:MAST, Cheddar, aiT WCET Analyzer, RapiTime and Inchron chronSUITE, in free, academic or evaluation versions.
Master's Thesis with defence:A complete timing analysis of a real-time system, from WCET estimation to schedulability analysis and certification evidence, defended before a panel.
Flexible format:100% online, no fixed timetables, compatible with full-time work.
Capstone project

Build it end to end

Your final project follows the real engineering workflow, step by step, reviewed by your tutor.

Response-time analysis
Analyse the response times of a multitasking system with MAST.
WCET calculation
Calculate worst-case execution times with aiT and validate the bounds.
Multicore interference measurement
Measure and mitigate inter-core interference using microbenchmarks.
ARINC 653 partition table
Design a partition schedule with temporal and spatial isolation.
Master's Thesis
A complete timing analysis and evidence dossier for a real-time system, defended before a panel.
Career opportunities

Where this takes you

Real-time systems engineerTiming analystCritical software engineerEmbedded software architectFunctional safety engineerTiming verification engineer
Admissions & scholarships

Requirements

  • University degree in engineering, science or architecture, or equivalent demonstrable professional experience.
  • Internet connection and a computer capable of running the programme software.
  • English sufficient to read technical standards.

Ready to start?

Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.

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FAQ

Frequently asked questions

The programme totals 1,900 hours over 12–14 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.

You work with MAST, Cheddar, aiT WCET Analyzer, RapiTime and Inchron chronSUITE, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.

A SEIUM Institute diploma, awarded on passing the continuous assessment and the Master's Thesis. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.

Yes. Modules passed in a course or postgraduate diploma in the same area are recognised in the higher programme. Ask about the recognition policy when you enrol.

A university degree in engineering, science or architecture (or equivalent professional experience), a computer able to run the programme software, and English sufficient to read technical standards.

Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.

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