Master’s in Heterogeneous Computing for AD (CPU/GPU/NPU)
Online master's programme of 1,900 hours in heterogeneous computing for autonomous driving (CPU/GPU/NPU). 12 modules covering GPU programming, neural network inference, task scheduling, memory, power and thermal management and functional safety under ISO 26262, ISO 21448 and ISO/PAS 8800, with an assigned technical tutor.
Take the controls.
Run a real engineering trade-off from this field. Move the sliders, watch the model react in real time and beat the challenge.
What you will be able to do
Characterise the computing workloads of autonomous driving.
Compare CPU, GPU and NPU architectures.
Program compute kernels on GPUs.
Optimise neural network inference on embedded hardware.
Schedule tasks on heterogeneous systems with timing requirements.
Manage the platform's memory, power consumption and thermal behaviour.
Apply functional safety requirements to accelerated computing.
Who it's for
- Heterogeneous computing engineers looking to focus on autonomous driving platforms.
- Inference optimisation engineers working with embedded neural networks.
- GPU programmers who want to move into automotive applications.
- Autonomous driving platform architects.
- Embedded systems engineers.
- Performance engineers.
- Engineering or science graduates seeking to enter the autonomous driving sector.
What you'll work with
- ISO 26262 (functional safety)
- ISO 21448 (SOTIF – safety of the intended functionality)
- ISO/PAS 8800 (artificial intelligence in road vehicles)
- UL 4600 (safety of autonomous products)
- ISO/SAE 21434 (vehicle cybersecurity)
- MISRA C++:2023 (coding guidelines for C++)
- NVIDIA CUDA Toolkit
- NVIDIA TensorRT
- NVIDIA Nsight Systems
- ONNX Runtime
- OpenCL
12 modules
1.1Perception, fusion, planning and control chain1.2Latency and throughput requirements per stage1.3Computing profile of each task1.4Sensors and volume of data generated1.5Power and heat dissipation budget1.6Cost per vehicle and scaling1.7Realistic performance metrics1.8Common bottlenecks1.9Sizing criteria1.10Workshop: workload profile of an AD system
2.1Multi-core CPUs and memory hierarchy2.2GPU: execution model and occupancy2.3NPUs and inference accelerators2.4DSPs and ISPs in the vision chain2.5FPGAs and where they fit2.6Interconnect and bandwidth2.7Shared memory and coherence2.8Commercial automotive platforms2.9Performance-per-watt comparison2.10Lab: characterisation of a platform
3.1Threads, blocks and grids model3.2Global memory, shared memory and registers3.3Coalescing and access patterns3.4Divergence and occupancy3.5Streams and overlapping of computation and transfer3.6Synchronisation and events3.7Profiling and key metrics3.8Iterative optimisation of a kernel3.9Portability across platforms3.10Lab: optimisation of a vision kernel
4.1From trained model to deployed model4.2Computation graphs and operator fusion4.3INT8 quantisation and calibration4.4Pruning and distillation4.5Exchange formats and compilers4.6Inference engines and their limitations4.7Accuracy versus latency4.8Validating degradation after quantisation4.9Managing multiple models4.10Lab: quantisation and accuracy measurement
5.1Assigning tasks to computing units5.2Priorities and pre-emption on accelerators5.3End-to-end pipeline latency5.4Task and data parallelism5.5Queues, buffers and back-pressure5.6Interference between workloads5.7Determinism and worst case5.8Allocation of memory and bandwidth5.9Runtime monitoring5.10Lab: scheduling a pipeline
6.1ISP chain and pre-processing6.2Intensive operations and their cost6.3Accelerating convolutions6.4Point cloud processing6.5Early and late fusion6.6Compression and transport of sensor data6.7Calibration and rectification6.8Synchronisation between cameras and lidar6.9Measuring output quality6.10Lab: accelerated vision pipeline
7.1Host-to-device copies7.2Unified memory and its pitfalls7.3Zero copy and buffer mapping7.4Alignment and block sizes7.5Managing memory peaks7.6Fragmentation and allocators7.7Memory budget per function7.8Leak diagnosis7.9Impact on total latency7.10Lab: eliminating redundant copies
8.1Dynamic and static power8.2Clock states and frequency scaling8.3Thermal limits and throttling8.4Cooling design for the computer8.5Ageing and silicon reliability8.6Transient errors and detection8.7Redundancy and voting8.8Temperature-driven degraded modes8.9In-vehicle measurement8.10Workshop: thermal and power budget
9.1ASIL requirements applied to accelerators9.2Hardware diagnostics and coverage9.3SoC safety mechanisms9.4Partitioning and freedom from interference9.5Output plausibility monitors9.6Independent safety channel9.7Evidence from the silicon vendor9.8Known limitations and their management9.9Safety argument9.10Workshop: analysis of an SoC for ASIL
10.1Instrumenting the pipeline10.2GPU and NPU traces10.3Measuring latency per stage10.4Detecting jitter and spikes10.5Benchmark automation10.6Comparison between versions10.7Performance regressions in continuous integration10.8Representativeness of scenarios10.9Reports for the team10.10Lab: performance dashboard
11.1Packaging models and binaries11.2Joint versioning of model and software11.3Updating models across the fleet11.4Pre-deployment validation11.5Inference telemetry11.6Data drift detection11.7Retraining and life cycle11.8Managing heterogeneous hardware across the fleet11.9Platform obsolescence11.10Case study: updating a model
12.1Defining the function and its requirements12.2Choosing the platform and justifying it12.3Pipeline design and task allocation12.4Optimising the critical kernels12.5Quantisation and accuracy validation12.6Measuring latency and power consumption12.7Functional safety analysis12.8Deployment and monitoring plan12.9Technical report and defence12.10Master's Thesis: final review with the tutor
How you'll learn
100% online training on the SEIUM campus, with downloadable material, recorded classes and an assigned technical tutor. There are no fixed timetables: you progress at your own pace within each intake, which makes the programme compatible with work.
Each module combines theory, guided reading of the original standard and applied exercises. The working software is NVIDIA CUDA Toolkit, NVIDIA TensorRT, NVIDIA Nsight Systems, ONNX Runtime and OpenCL, in free, academic or evaluation versions. Testing is studied through real procedures for profiling inference on embedded platforms, power and temperature measurements and end-to-end latency tests. Assessment is continuous for each module, plus the final Master's Thesis.
Standards covered: ISO 26262, ISO 21448 (SOTIF), ISO/PAS 8800, UL 4600, ISO/SAE 21434 and MISRA C++:2023.
Build it end to end
Your final project follows the real engineering workflow, step by step, reviewed by your tutor.
Where this takes you
Requirements
- A university degree in engineering, science or architecture, or equivalent demonstrable professional experience.
- An internet connection and a computer capable of running the programme's software.
- English sufficient to read technical standards.
Ready to start?
Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.
Frequently asked questions
The programme totals 1,900 hours over 12–14 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.
You will work with NVIDIA CUDA Toolkit, NVIDIA TensorRT, NVIDIA Nsight Systems, ONNX Runtime and OpenCL. Free, academic or evaluation versions are used, and your tutor indicates the free alternative where one exists.
A SEIUM Institute diploma, awarded on passing the continuous assessment and the Master's Thesis. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.
Yes. Modules passed in a course or postgraduate diploma in the same area are recognised in the higher programme. Ask about the recognition policy when you enrol.
A university degree in engineering, science or architecture, or equivalent professional experience; an internet connection and a computer capable of running the software; and English sufficient to read technical standards.
Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.
Related programmes
Master’s in Visual-Inertial Odometry & Precise Positioning Engineering
Online master's programme of 1,900 hours in visual-inertial odometry and precise positioning engineering, structured in 12 modules covering state estimation, inertial sensors, geometric vision, VIO, high-precision…
Master’s in Diagnostics, Telemetry and Edge Analytics Engineering
Online master's programme of 1,900 hours in diagnostics, telemetry and edge analytics engineering, structured in 12 modules covering on-board diagnostics, vehicle telemetry, edge analytics, cloud data…
Master’s in UX Engineering for Robotaxis and Autonomous Shuttles
Online master's programme of 1,900 hours in UX engineering for robotaxis and autonomous shuttles: 12 modules covering user research, booking apps, boarding, the on-board experience, trust,…
More in Autonomous, ADAS & Software-Defined Vehicle
All Autonomous, ADAS & Software-Defined Vehicle programmes → · How to apply · Fees & financing · Scholarships