Postgraduate Diploma in Deterministic Design in OT
Online Postgraduate Diploma of 800 h in Deterministic Design in OT. 8 modules covering IEC 61131-3, IEC 61499 and CODESYS. Assigned tutor and open enrolment.
Take the controls.
Run a real engineering trade-off from this field. Move the sliders, watch the model react in real time and beat the challenge.
What you will be able to do
Understand real-time requirements in OT systems.
Analyse the schedulability of task sets.
Configure deterministic platforms based on RTOS and Linux.
Programme control applications with bounded execution.
Design communications with guaranteed end-to-end latency.
Verify and validate the system's timing behaviour.
Evaluate converged virtualised control architectures.
Who it's for
- Real-time control engineer who wants to specialise in Deterministic Design in OT.
- Embedded systems engineer who wants to specialise in Deterministic Design in OT.
- Advanced PLC programmer who wants to specialise in Deterministic Design in OT.
- Automation architect who wants to specialise in Deterministic Design in OT.
- Validation engineer who wants to specialise in Deterministic Design in OT.
- Industrial software engineer who wants to specialise in Deterministic Design in OT.
- Graduates in engineering or science looking to enter manufacturing.
What you'll work with
- IEC 61131-3
- IEC 61499
- IEEE 802.1Qbv
- IEEE 1588-2019
- IEC 61784-2
- IEC 61508
- ARINC 653
8 modules · 800 h
1.1Hard and soft real time1.2Deadlines, periods and jitter1.3Closed-loop control requirements1.4Sources of non-determinism1.5Worst-case execution time WCET1.6Periodic and sporadic task models1.7PLC cycles and scan times1.8Distributed control architectures1.9Relationship between determinism and safety1.10Practical: measuring jitter in a control cycle
2.1Fixed-priority scheduling2.2Rate monotonic and deadline monotonic2.3Earliest deadline first2.4Response-time analysis2.5Priority inversion and protocols2.6Static cyclic scheduling2.7ARINC 653 temporal partitioning2.8Timing analysis tools2.9Margins and design robustness2.10Workshop: schedulability analysis of tasks
3.1Real-time operating systems3.2Linux with PREEMPT_RT3.3Real-time hypervisors3.4CPU affinity and core isolation3.5Interrupts and kernel latencies3.6Cache and memory effects3.7Multicore and interference3.8Software PLCs and virtual controllers3.9Measurement with cyclictest3.10Laboratory: tuning PREEMPT_RT
4.1IEC 61131-3 execution model4.2Cyclic, event-driven and free-running tasks4.3Function block design4.4Distributed IEC 61499 applications4.5Memory management and static allocation4.6Avoiding loops and unbounded operations4.7Inter-task communication4.8Unit testing on PLCs4.9Design patterns for control4.10Practical: distributed IEC 61499 application
5.1Isochronous fieldbuses5.2Real-time industrial Ethernet5.3TSN and time-aware scheduling5.4IEEE 1588 clock synchronisation5.5End-to-end latency budget5.6Synchronised motion and distributed control5.7Mixed traffic and isolation5.8Seamless redundancy5.9Diagnostics of deterministic communication5.10Laboratory: latency budget of a loop
6.1Verifiable timing requirements6.2Traces and logic analysers6.3Software timing instrumentation6.4Stress and load testing6.5Simulation and hardware-in-the-loop6.6Timing fault injection6.7Statistical analysis of latencies6.8Relationship with IEC 61508 and safety6.9Evidence for certification6.10Case study: timing validation of a controller
7.1Virtualised control on edge servers7.2Orchestration of control workloads7.3Real-time containers7.4IT and OT coexistence on the same hardware7.5Cloud control model and its limits7.6Controller redundancy7.7Cybersecurity without losing determinism7.8Migration of legacy systems7.9Trends in open automation7.10Practical: virtual PLC in a container
8.1Use case and timing requirements8.2Selection of control platform8.3Task design and scheduling8.4Communication design8.5Prototype implementation8.6Latency and jitter measurements8.7Analysis of results8.8Deployment recommendations8.9Thesis and presentation8.10Final review with the tutor
How you'll learn
100 % online training on the SEIUM campus, with downloadable material, recorded classes and assigned technical tutor. No fixed timetables: students progress at their own pace within the intake, making it possible to combine with work.
Each module combines theory, guided reading of the original standard and applied exercises. The working software is CODESYS, Beckhoff TwinCAT 3, Eclipse 4diac IDE, Linux PREEMPT_RT, rt-tests (cyclictest), in free, academic or evaluation versions. Tests are studied using real procedures for measuring cycle jitter, network-load stress testing and timing validation in hardware-in-the-loop. Assessment is continuous per module plus the final integrating project.
Build it end to end
Your final project follows the real engineering workflow, step by step, reviewed by your tutor.
Understand real-time requirements in OT systems.
Analyse the schedulability of task sets.
Configure deterministic platforms based on RTOS and Linux.
Programme control applications with bounded execution.
Design communications with guaranteed end-to-end latency.
Where this takes you
Requirements
- Prior technical training or professional experience in the sector. No university degree is required.
- Internet connection and a computer capable of running the programme's software.
- Sufficient command of Spanish to follow technical standards reading material.
Ready to start?
Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.
Frequently asked questions
The programme consists of 800 hours in total, spread over 6 to 8 months. That is between 10 and 15 hours per week on average, compatible with a full-time job.
You work with CODESYS, Beckhoff TwinCAT 3, Eclipse 4diac IDE, Linux PREEMPT_RT, rt-tests (cyclictest). Free, academic or evaluation versions are used, and the tutor indicates the free alternative where one exists.
A SEIUM own diploma upon passing continuous assessment and the integrating project. This is in-house training, not an official qualification from the Ministry.
Yes. Modules passed in a course or postgraduate diploma in the same area are recognised towards the higher programme. Check the recognition policy when you enrol.
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