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Master'sElectromobility, Batteries & Hydrogen Applications open

Master’s in SiC/GaN Power Electronics for e-Mobility

Online master's programme of 1,900 hours in SiC/GaN power electronics for e-mobility, structured in 12 modules covering wide-bandgap devices, loss characterisation, gate drives, power stage design, topologies, thermal management, digital control, EMC, reliability and vehicle integration, with an assigned technical tutor.

Duration1900 h
ModeOnline
LanguageEnglish
Start datesSet by the faculty
AwardSEIUM Institute diploma
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Learning outcomes

What you will be able to do

01

Compare the properties of SiC and GaN semiconductors with silicon.

02

Characterise conduction and switching losses using the double-pulse test.

03

Design gate drive circuits for fast switching.

04

Select converter topologies for traction and charging.

05

Size the thermal management of power modules.

06

Mitigate EMC problems in high-speed switching converters.

07

Plan reliability qualification in accordance with AQG 324 and AEC-Q101.

Profile

Who it's for

  • Power electronics engineers moving to SiC and GaN devices.
  • Inverter design engineers in electric vehicle programmes.
  • Wide-bandgap semiconductor engineers working on applications.
  • Electromagnetic compatibility engineers dealing with fast-switching converters.
  • Power module reliability engineers.
  • Digital control engineers for power converters.
  • Engineering or science graduates aiming to enter the automotive industry.
Standards & tools

What you'll work with

  • AQG 324 (qualification of power modules for automotive use)
  • AEC-Q101 (qualification of discrete semiconductors)
  • CISPR 25 (radio emissions from vehicle components)
  • JEDEC JESD22-A108 (high-temperature operating life)
  • IEC 60664-1 (insulation coordination)
  • ISO 16750 (environmental conditions for vehicle electrical equipment)
  • ISO 26262 (automotive functional safety)
  • UN R10 (electromagnetic compatibility of vehicles)
  • PLECS
  • LTspice
  • Ansys Q3D Extractor
  • Ansys Icepak
  • MATLAB/Simulink
Syllabus

12 modules · 1900 h

  1. 1.1Properties of SiC and GaN
  2. 1.2Comparison with silicon
  3. 1.3Voltage, temperature and frequency limits
  4. 1.4MOSFET and HEMT structures
  5. 1.5Reliability and degradation modes
  6. 1.6Availability and cost
  7. 1.7Specific packages
  8. 1.8Selection by application
  9. 1.9Datasheet: critical reading
  10. 1.10Workshop: device comparison
  1. 2.1Conduction and switching losses
  2. 2.2Measurement of fast waveforms
  3. 2.3Probes and required bandwidth
  4. 2.4Double-pulse testing and its set-up
  5. 2.5Switching energies
  6. 2.6Effect of temperature
  7. 2.7Device parasitic capacitances
  8. 2.8Comparison between manufacturers
  9. 2.9Models for simulation
  10. 2.10Laboratory: double-pulse test
  1. 3.1Driver requirements for SiC and GaN
  2. 3.2Gate voltages and margins
  3. 3.3Gate resistors and trade-offs
  4. 3.4Driver isolation
  5. 3.5dv/dt immunity
  6. 3.6Desaturation protection
  7. 3.7Soft turn-off under fault
  8. 3.8Driver power supply
  9. 3.9Physical layout of the driver
  10. 3.10Laboratory: design and testing of a driver
  1. 4.1Parasitic inductances of the switching loop
  2. 4.2PCB and busbar design
  3. 4.3Decoupling capacitors
  4. 4.4Device placement
  5. 4.5Overvoltage measurement
  6. 4.6Snubbers and their cost
  7. 4.7Paralleling of devices
  8. 4.8Current sharing
  9. 4.9Design verification
  10. 4.10Laboratory: loop optimisation
  1. 5.1Three-phase traction inverter
  2. 5.2High-power DC-DC converters
  3. 5.3On-board chargers
  4. 5.4Multilevel topologies
  5. 5.5Resonant converters
  6. 5.6Selection according to bus voltage
  7. 5.7Achievable efficiency
  8. 5.8Power density
  9. 5.9Comparison of architectures
  10. 5.10Laboratory: topology simulation
  1. 6.1Thermal resistances and paths
  2. 6.2Ceramic substrates and packaging
  3. 6.3Direct and indirect cooling
  4. 6.4Thermal cycling and solder fatigue
  5. 6.5Junction temperature measurement
  6. 6.6Compact thermal modelling
  7. 6.7Derating and design limits
  8. 6.8Thermal interface materials
  9. 6.9Thermal validation
  10. 6.10Laboratory: thermal measurement of a module
  1. 7.1PWM modulation and its resolution
  2. 7.2Current and voltage loops
  3. 7.3Synchronous sampling and delays
  4. 7.4Microcontrollers and FPGAs
  5. 7.5Protections implemented in software
  6. 7.6Compensation and stability
  7. 7.7Development tools
  8. 7.8Control validation
  9. 7.9Functional safety of the control
  10. 7.10Laboratory: implementation of a loop
  1. 8.1Spectrum generated by fast switching
  2. 8.2Common mode and parasitic currents
  3. 8.3Filtering and shielding
  4. 8.4Designing for EMC from the outset
  5. 8.5Emissions measurement
  6. 8.6Common fixes and their cost
  7. 8.7Speed versus noise trade-off
  8. 8.8Applicable regulations
  9. 8.9Pre-certification testing
  10. 8.10Laboratory: emissions measurement
  1. 9.1Failure modes of SiC and GaN
  2. 9.2AEC-Q qualification tests
  3. 9.3Accelerated life tests
  4. 9.4Humidity and bias
  5. 9.5Cosmic rays and random failures
  6. 9.6Degradation detection
  7. 9.7Design for reliability
  8. 9.8Warranties and field data
  9. 9.9Failure analysis
  10. 9.10Case study: qualification plan
  1. 10.1Cost per ampere and per watt
  2. 10.2Price trends
  3. 10.3Availability and second sources
  4. 10.4Design for substitutability
  5. 10.5Impact of packaging on cost
  6. 10.6Volume and negotiation
  7. 10.7Supply risks
  8. 10.8Choosing between silicon and wide-bandgap
  9. 10.9Business case
  10. 10.10Workshop: total cost analysis
  1. 11.1Location of the converter
  2. 11.2Power and control connections
  3. 11.3Shared cooling
  4. 11.4Audible noise and vibration
  5. 11.5Maintenance and diagnostics
  6. 11.6High-voltage safety
  7. 11.7In-vehicle testing
  8. 11.8Validation under real conditions
  9. 11.9After-sales and spare parts
  10. 11.10Case study: integration of an inverter
  1. 12.1Specification and requirements
  2. 12.2Selection of devices and topology
  3. 12.3Design of the driver and power stage
  4. 12.4Thermal and mechanical design
  5. 12.5Digital control and protections
  6. 12.6Test and EMC plan
  7. 12.7Results and measured efficiency
  8. 12.8Cost and reliability analysis
  9. 12.9Technical report and defence
  10. 12.10Master's Thesis: final review with the tutor
Methodology, software & labs

How you'll learn

100% online training on the SEIUM campus, with downloadable material, recorded classes and an assigned technical tutor. There are no fixed timetables: you progress at your own pace within each intake, so the programme can be combined with work.

Each module combines theory, guided reading of the original standard and applied exercises. The working software is PLECS, LTspice, Ansys Q3D Extractor, Ansys Icepak and MATLAB/Simulink, in free, academic or evaluation versions. Testing is studied through real procedures: double-pulse testing, switching loss characterisation and electromagnetic compatibility measurements on converters. Assessment is continuous by module, plus the final Master's Thesis.

Standards covered: AQG 324, AEC-Q101, CISPR 25, JEDEC JESD22-A108, IEC 60664-1, ISO 16750, ISO 26262 and UN R10.

Assigned technical tutor:every module ends with a deliverable that your tutor marks individually.
Standards-based learning:guided reading of AQG 324, AEC-Q101 and CISPR 25 applied to real cases, not as a theoretical annex.
Industry software:PLECS, LTspice, Ansys Q3D Extractor, Ansys Icepak and MATLAB/Simulink, in free, academic or evaluation versions.
Master's Thesis with defence:a complete SiC/GaN converter project, from device and topology selection to measured efficiency, EMC and reliability analysis, defended before a panel.
Flexible format:100% online, no fixed timetables, compatible with full-time work.
Capstone project

Build it end to end

Your final project follows the real engineering workflow, step by step, reviewed by your tutor.

Specification and device selection
Define the requirements and select SiC/GaN devices and topology.
Driver and power stage
Design the gate driver and a low-inductance power stage.
Thermal and mechanical design
Size cooling, substrates and thermal paths of the converter.
Control and EMC
Implement digital control and protections and plan the EMC tests.
Master's Thesis
Measured efficiency, cost and reliability analysis and technical report, defended before a panel.
Career opportunities

Where this takes you

Power electronics engineerInverter design engineerWide-bandgap semiconductor engineerElectromagnetic compatibility engineerPower module reliability engineerConverter digital control engineer
Admissions & scholarships

Requirements

  • University degree in engineering, science or architecture, or equivalent demonstrable professional experience.
  • Internet connection and a computer capable of running the programme software.
  • English sufficient to read technical standards.

Ready to start?

Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.

Apply now Scholarships
FAQ

Frequently asked questions

The programme totals 1,900 hours over 12–14 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.

You work with PLECS, LTspice, Ansys Q3D Extractor, Ansys Icepak and MATLAB/Simulink, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.

A SEIUM Institute diploma, awarded on passing the continuous assessment and the Master's Thesis. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.

Yes. Modules passed in a course or postgraduate diploma in the same area are recognised in the higher programme. Ask about the recognition policy when you enrol.

A university degree in engineering, science or architecture (or equivalent professional experience), a computer able to run the software and English sufficient to read technical standards.

Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.

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