Master’s in High-Speed Data Conversion Engineering
Online master's programme of 1,900 hours in high-speed data conversion engineering. 12 modules covering converter metrics, ADC and DAC architectures, analogue front-ends, clocks and jitter, JESD204 interfaces, RF direct sampling, converter board design, associated DSP and characterisation to IEEE 1241 and IEEE 1658, with an assigned technical tutor.
Take the controls.
Run a real engineering trade-off from this programme. Move the sliders, watch the model react in real time and beat the challenge.
What you will be able to do
Analyse the static and dynamic metrics of data converters.
Select ADC and DAC architectures for each application.
Design conditioning, filtering and driver chains for converters.
Manage the sampling clock and its impact on jitter.
Integrate converters with FPGAs through JESD204 interfaces.
Apply direct RF sampling techniques.
Characterise converters in the laboratory using standardised methods.
Who it's for
- Data conversion engineers working with high-speed ADCs and DACs.
- Mixed-signal design engineers moving into high-speed acquisition.
- RF hardware engineers adopting direct-sampling architectures.
- Converter applications engineers supporting customer designs.
- High-speed instrumentation engineers building digitisers and test equipment.
- Systems validation engineers characterising acquisition chains.
- Engineering or science graduates seeking to move into telecommunications.
What you'll work with
- IEEE 1241 (terminology and test methods for analogue-to-digital converters)
- IEEE 1658 (terminology and test methods for digital-to-analogue converters)
- JEDEC JESD204C (serial interface for data converters)
- IEEE 1057 (digitising waveform recorders)
- ETSI TS 138 104 (5G NR base station radio transmission and reception)
- IEC 61000-4-2 (electrostatic discharge immunity)
- VITA 57.4 FMC+ (FPGA mezzanine card standard)
- IPC-2141A (controlled-impedance design)
- MATLAB and Mixed-Signal Blockset
- Keysight ADS
- Analog Devices ACE
- AMD Vivado
- LTspice
12 modules · 1900 h
1.1Sampling, aliasing and Nyquist zones1.2Quantisation and quantisation noise1.3Ideal SNR and effective number of bits1.4Oversampling and noise shaping1.5Undersampling1.6Code representation and formats1.7Analogue bandwidth versus sample rate1.8Applications of high-speed converters1.9Converter market trends1.10Case study: converter selection for a spectrum analyser
2.1Offset and gain errors2.2Differential and integral non-linearity2.3SNR, SINAD and ENOB2.4Harmonic distortion and SFDR2.5Intermodulation products2.6Phase noise and aperture jitter2.7Noise spectral density2.8Metrics according to IEEE 12412.9Interpreting datasheets2.10Practical: calculating ENOB from an FFT
3.1Flash converters and their power consumption3.2Successive-approximation (SAR) converters3.3Pipeline converters3.4Continuous-time sigma-delta converters3.5Time-interleaved converters3.6Mismatches in interleaved converters3.7Digital background calibration3.8Comparison by figure of merit3.9Architecture selection by application3.10Lab: model of a pipeline ADC in MATLAB
4.1Current-source architectures4.2Segmented DACs and thermometer coding4.3Sinc response and equalisation4.4Digital interpolation in the DAC4.5Return-to-zero and mix modes4.6Dynamic errors and glitches4.7Reconstruction filtering4.8DACs for direct RF synthesis4.9Metrics according to IEEE 16584.10Workshop: multitone signal generation with a DAC
5.1ADC driver amplifiers5.2DC and AC coupling5.3Wideband transformers and baluns5.4Input anti-aliasing filters5.5Impedance matching5.6Dynamic range of the signal chain5.7Input protection5.8Noise and distortion budget5.9Simulation of the complete chain5.10Practical: design of an ADC driver stage
6.1Effect of jitter on SNR6.2Sources of random and deterministic jitter6.3Crystal oscillators and VCXOs6.4Low-noise PLL synthesisers6.5Jitter cleaners and clock distribution6.6Phase noise measurement6.7Synchronisation of multiple converters6.8SYSREF signal and determinism6.9Clock routing on the board6.10Lab: jitter budget for a digitiser
7.1Evolution from LVDS to JESD2047.2JESD204B and JESD204C layers7.38b/10b and 64b/66b encoding7.4Deterministic latency in subclass 17.5Link parameter configuration7.6JESD204 cores in FPGAs7.7Serial link debugging7.8Lane signal integrity7.9Multichannel synchronisation across devices7.10Workshop: JESD204B link between ADC and FPGA
8.1Direct-sampling receiver architectures8.2RF converters and their bandwidth8.3Digital down-conversion8.4Numerically controlled oscillators and digital mixers8.5On-converter decimation filters8.6Integrated RFSoC platforms8.7Applications in 5G and radar8.8Frequency planning and spurs8.9Multichannel calibration8.10Case study: L-band direct-sampling receiver
9.1Grounding and planes in mixed-signal systems9.2Decoupling of converter supplies9.3Low-noise regulators9.4Isolation between digital and analogue9.5Routing of differential inputs9.6Thermal management of high-speed converters9.7FMC cards and evaluation boards9.8Sources of spurs on the board9.9Board design review9.10Practical: review of an evaluation board
10.1Correction of interleaving errors10.2Digital channel equalisation10.3Decimation and interpolation filters10.4Digital linearisation of the chain10.5Averaging and detection10.6Real-time FPGA processing10.7Handling large data streams10.8Storage and transfer10.9Algorithms for radar and communications10.10Lab: mismatch correction in an interleaved ADC
11.1Converter test benches11.2High-purity signal generators11.3Narrowband filters for testing11.4Coherent sampling and windowing11.5Histogram-based linearity measurement11.6SFDR and intermodulation measurement11.7Temperature and variation tests11.8Measurement automation11.9Characterisation report11.10Case study: characterisation of a 14-bit ADC
12.1Definition of the acquisition system12.2Converter selection12.3Analogue chain design12.4Sampling clock design12.5Digital integration with an FPGA12.6Associated digital processing12.7System characterisation12.8Conclusions and future work12.9Master's Thesis report12.10Master's Thesis: defence before a panel
How you'll learn
Training is 100% online on the SEIUM campus, with downloadable material, recorded classes and an assigned technical tutor. There are no fixed timetables: you progress at your own pace within the intake, so it fits around your job.
Each module combines theory, guided reading of the original standard and applied exercises. The working software is MATLAB and Mixed-Signal Blockset, Keysight ADS, Analog Devices ACE, AMD Vivado and LTspice, in free, academic or evaluation versions. Work is based on real procedures: FFT-based dynamic characterisation of converters, design of a digitiser's analogue signal chain and JESD204 integration between converter and FPGA. Assessment is continuous per module, plus the final Master's Thesis.
Standards covered: IEEE 1241, IEEE 1658, JEDEC JESD204C, IEEE 1057, ETSI TS 138 104, IEC 61000-4-2, VITA 57.4 FMC+, IPC-2141A.
Build it end to end
Your final project follows the real engineering workflow, step by step, reviewed by your tutor.
Where this takes you
Requirements
- University degree in engineering, science or architecture, or equivalent demonstrable professional experience.
- Internet connection and a computer capable of running the programme software.
- English sufficient to read technical standards.
Ready to start?
Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.
Frequently asked questions
The programme totals 1,900 hours over 12–14 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.
You work with MATLAB and Mixed-Signal Blockset, Keysight ADS, Analog Devices ACE, AMD Vivado and LTspice, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.
A SEIUM Institute diploma, awarded on passing the continuous assessment and the Master's Thesis. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.
Yes. Modules passed in a course or postgraduate diploma in the same area are recognised in the higher programme. Ask about the recognition policy when you enrol.
A university degree in engineering, science or architecture (or equivalent professional experience), a computer able to run the programme software, and English sufficient to read technical standards.
Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.
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