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Master’s in DO-254 and FPGA/ASIC Certification Engineering

Online master's programme of 1,900 hours in DO-254 engineering and FPGA/ASIC certification, structured in 12 modules covering hardware planning, requirements, HDL design, implementation, functional and advanced verification, tool qualification, COTS, reliability and configuration management, with an assigned technical tutor.

Duration1900 h
ModeOnline
LanguageEnglish
Start datesSet by the faculty
AwardSEIUM Institute diploma
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Learning outcomes

What you will be able to do

01

Understand the scope of DO-254 and the classification of complex hardware.

02

Plan the hardware life cycle in accordance with DO-254.

03

Specify verifiable and traceable hardware requirements.

04

Design and implement FPGA and ASIC devices using good practice.

05

Apply functional and advanced verification methods.

06

Manage COTS components and qualified tools.

07

Prepare audits and hardware accomplishment summaries.

Profile

Who it's for

  • Airborne hardware engineers moving into DO-254 certification work.
  • FPGA designers working on safety-critical avionics devices.
  • Hardware verification engineers looking to master UVM, formal methods and coverage for DAL A/B.
  • DO-254 certification engineers seeking deeper technical grounding in design and verification.
  • ASIC design engineers entering the aerospace market.
  • Process assurance managers responsible for hardware programmes.
  • Engineering or science graduates aiming to join avionics suppliers.
Standards & tools

What you'll work with

  • RTCA DO-254 / EUROCAE ED-80 (design assurance guidance for airborne electronic hardware)
  • AMC 20-152A (EASA acceptable means of compliance for airborne electronic hardware)
  • SAE ARP4754A (development of civil aircraft and systems)
  • AMC 20-193 (use of multicore processors)
  • RTCA DO-160G (environmental conditions and test procedures for airborne equipment)
  • IEEE 1800-2017 SystemVerilog (hardware design and verification language)
  • IEEE 1076-2019 VHDL (hardware description language)
  • SAE ARP4761A (safety assessment process for civil aircraft)
  • Questa Advanced Simulator
  • AMD Vivado
  • Synopsys Design Compiler
  • IBM DOORS
  • Siemens HDL Designer
Syllabus

12 modules · 1900 h

  1. 1.1Classification of simple and complex hardware
  2. 1.2PLD, FPGA and ASIC devices in avionics
  3. 1.3Airborne hardware life cycle
  4. 1.4Relationship between DO-254 and ARP4754A
  5. 1.5DAL assignment to hardware
  6. 1.6AMC 20-152A and its scope
  7. 1.7Differences between SRAM, flash and antifuse FPGAs
  8. 1.8Typical functions implemented in FPGAs
  9. 1.9Lessons from certification findings
  10. 1.10Case study: classification of the devices on a circuit board
  1. 2.1Plan for Hardware Aspects of Certification (PHAC)
  2. 2.2Hardware design plan
  3. 2.3Validation and verification plan
  4. 2.4Configuration management plan
  5. 2.5Process assurance plan
  6. 2.6Requirements and design standards
  7. 2.7Transition criteria between phases
  8. 2.8Hardware stages of involvement
  9. 2.9Management of hardware suppliers
  10. 2.10Workshop: writing a PHAC for an engine controller
  1. 3.1Capturing requirements from the system
  2. 3.2Derived requirements and their feedback
  3. 3.3Verifiable and unambiguous requirements
  4. 3.4Validation of hardware requirements
  5. 3.5Bidirectional traceability with DOORS
  6. 3.6Design safety requirements
  7. 3.7Timing and interface requirements
  8. 3.8Management of requirement changes
  9. 3.9Formal requirements reviews
  10. 3.10Practical exercise: requirements specification for an ARINC 429 decoder
  1. 4.1Functional architecture of the device
  2. 4.2VHDL and Verilog coding to standards
  3. 4.3Synchronous design rules
  4. 4.4Clock domains and synchronisers
  5. 4.5Safe state machines
  6. 4.6Reset and start-up management
  7. 4.7HDL code review
  8. 4.8Linting rules with tools
  9. 4.9Reuse of IP cores
  10. 4.10Lab: VHDL design of a fault-tolerant UART controller
  1. 5.1Logic synthesis and constraints
  2. 5.2Place and route
  3. 5.3Static timing analysis
  4. 5.4Power and thermal analysis
  5. 5.5Bitstream generation
  6. 5.6ASIC design flow
  7. 5.7Formal equivalence checking
  8. 5.8Tool version management
  9. 5.9Programming and production control
  10. 5.10Practical exercise: timing closure on an FPGA design
  1. 6.1Requirements-based simulation
  2. 6.2Self-checking testbenches with reference models
  3. 6.3UVM verification methodology
  4. 6.4Requirements and code coverage
  5. 6.5Robustness testing and corner cases
  6. 6.6In-board verification of the device
  7. 6.7At-speed testing
  8. 6.8Analysis of results and discrepancies
  9. 6.9Independence in verification
  10. 6.10Lab: UVM testbench with functional coverage
  1. 7.1Elemental analysis under DO-254
  2. 7.2Formal verification with model checking
  3. 7.3Assertion-based verification
  4. 7.4Structural coverage analysis of HDL
  5. 7.5Fault injection in simulation
  6. 7.6CDC and RDC analysis
  7. 7.7Verification of third-party IP
  8. 7.8Formal verification tools
  9. 7.9Combining methods for DAL A
  10. 7.10Case study: verification strategy for a DAL A device
  1. 8.1Design and verification tools
  2. 8.2Assessment under DO-254 section 11.4
  3. 8.3Tool service history
  4. 8.4Independent output assessment
  5. 8.5Synthesis and place-and-route tools
  6. 8.6Simulation tools
  7. 8.7Qualification documentation
  8. 8.8Management of known errors
  9. 8.9Relationship with DO-330
  10. 8.10Practical exercise: assessment of the synthesis tool
  1. 9.1COTS IP and its assessment
  2. 9.2Use of complex microcontrollers
  3. 9.3Multicore processors under AMC 20-193
  4. 9.4Component service history
  5. 9.5Errata sheets and their management
  6. 9.6Component obsolescence
  7. 9.7Components with hidden functions
  8. 9.8Supply chain management
  9. 9.9Counterfeit components and mitigation
  10. 9.10Case study: justification of an SoC with an embedded processor
  1. 10.1Single event upsets in FPGAs
  2. 10.2Configuration scrubbing
  3. 10.3Triple modular redundancy
  4. 10.4Component reliability analysis
  5. 10.5Ageing and electromigration
  6. 10.6DO-160 environmental qualification
  7. 10.7Thermal and vibration effects
  8. 10.8Hardware FMEA
  9. 10.9Mitigation of latent faults
  10. 10.10Lab: implementing TMR on a critical register
  1. 11.1Identification of configuration items
  2. 11.2Hardware baselines
  3. 11.3Change control and problem reports
  4. 11.4Archiving and retrieval
  5. 11.5Hardware process assurance
  6. 11.6Hardware SOI audits
  7. 11.7Hardware Accomplishment Summary
  8. 11.8Production conformity
  9. 11.9Certification of modifications
  10. 11.10Workshop: preparing a SOI 3 audit
  1. 12.1Definition of the hardware function
  2. 12.2Requirements and assigned DAL
  3. 12.3Hardware certification plans
  4. 12.4HDL design of the device
  5. 12.5Implementation and timing
  6. 12.6Functional and advanced verification
  7. 12.7Configuration management
  8. 12.8Accomplishment summary
  9. 12.9Master's Thesis report
  10. 12.10Master's Thesis: defence before a panel
Methodology, software & labs

How you'll learn

100% online training on the SEIUM campus, with downloadable material, recorded classes and an assigned technical tutor. No fixed timetables: you progress at your own pace within the intake, so it fits alongside your job.

Each module combines theory, guided reading of the original standard and applied exercises. The working software is Questa Advanced Simulator, AMD Vivado, Synopsys Design Compiler, IBM DOORS and Siemens HDL Designer, in free, academic or evaluation versions. Testing is studied through real procedures for UVM verification of FPGA devices, static timing analysis and hardware certification audits. Assessment is continuous by module, plus the final Master's Thesis.

Standards covered: RTCA DO-254 / EUROCAE ED-80, AMC 20-152A, SAE ARP4754A, AMC 20-193, RTCA DO-160G, IEEE 1800-2017 SystemVerilog, IEEE 1076-2019 VHDL, SAE ARP4761A.

Assigned technical tutor:every module ends with a deliverable that your tutor marks individually.
Standards-based learning:guided reading of RTCA DO-254 / EUROCAE ED-80, AMC 20-152A and SAE ARP4754A applied to real cases, not as a theoretical annex.
Industry software:Questa Advanced Simulator, AMD Vivado, Synopsys Design Compiler, IBM DOORS and Siemens HDL Designer, in free, academic or evaluation versions.
Master's Thesis with defence:A complete DO-254 certification project for an FPGA/ASIC hardware function, from requirements and DAL through HDL design, verification and accomplishment summary, defended before a panel.
Flexible format:100% online, no fixed timetables, compatible with full-time work.
Capstone project

Build it end to end

Your final project follows the real engineering workflow, step by step, reviewed by your tutor.

Write the PHAC
Draft the Plan for Hardware Aspects of Certification for an engine controller.
Specify the requirements
Write verifiable, traceable requirements for an ARINC 429 decoder.
Design and close timing
Design a fault-tolerant HDL device and achieve timing closure on the FPGA.
Verify with UVM
Build a UVM testbench with functional coverage and a DAL A verification strategy.
Master's Thesis
A full DO-254 hardware certification project, from requirements to accomplishment summary, defended before a panel.
Career opportunities

Where this takes you

Airborne hardware engineerFPGA designerHardware verification engineerDO-254 certification engineerASIC design engineerProcess assurance manager
Admissions & scholarships

Requirements

  • A university degree in engineering, science or architecture, or equivalent demonstrable professional experience.
  • An internet connection and a computer capable of running the programme software.
  • English sufficient to read technical standards.

Ready to start?

Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.

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FAQ

Frequently asked questions

The programme totals 1,900 hours over 12–14 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.

You work with Questa Advanced Simulator, AMD Vivado, Synopsys Design Compiler, IBM DOORS and Siemens HDL Designer, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.

A SEIUM Institute diploma, awarded on passing the continuous assessment and the Master's Thesis. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.

Yes. Modules passed in a course or postgraduate diploma in the same area are recognised in the higher programme. Ask about the recognition policy when you enrol.

A university degree in engineering, science or architecture (or equivalent professional experience), a computer able to run the programme software, and English sufficient to read technical standards.

Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.

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