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Master'sElectronics, Embedded Systems & Telecom Applications open

Master’s in SoC/FPGA Architectures for Embedded Systems Engineering

Online master's programme of 1,900 hours in SoC/FPGA architecture engineering for embedded systems. 12 modules covering programmable logic architectures, RTL design in VHDL and SystemVerilog, AMBA AXI4 SoC integration, high-level synthesis, timing closure, UVM verification, hardware-software co-design, high-speed interfaces, reliability, AI acceleration and secure production, with an assigned technical tutor.

Duration1900 h
ModeOnline
LanguageEnglish
Start datesSet by the faculty
AwardSEIUM Institute diploma
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Learning outcomes

What you will be able to do

01

Design heterogeneous SoC architectures combining processors and programmable logic.

02

Describe synthesisable hardware in VHDL and SystemVerilog.

03

Integrate AXI interfaces, memories and peripherals into complex systems.

04

Apply high-level synthesis to accelerate algorithms.

05

Achieve timing closure while optimising resources and power.

06

Verify designs using simulation, assertion and coverage methodologies.

07

Develop software and drivers for SoC FPGA platforms.

Profile

Who it's for

  • FPGA design engineers.
  • SoC architecture engineers.
  • Hardware verification engineers.
  • Hardware-software co-design engineers.
  • Hardware accelerator engineers.
  • Embedded systems engineers moving into programmable logic.
  • Engineering or science graduates looking to enter the telecommunications sector.
Standards & tools

What you'll work with

  • AMBA AXI4 Protocol Specification (on-chip interconnect)
  • IEEE 1800 SystemVerilog (hardware description and verification language)
  • IEEE 1076 VHDL (hardware description language)
  • IEEE 1149.1 (JTAG boundary scan)
  • RTCA DO-254 (design assurance guidance for airborne electronic hardware)
  • IEEE 1735 (encryption and management of electronic design IP)
  • Accellera UVM 1.2 (Universal Verification Methodology)
  • IEC 61508 (functional safety of E/E/PE systems)
  • AMD Vivado
  • AMD Vitis
  • Intel Quartus Prime
  • Siemens Questa
  • Verilator
Syllabus

12 modules · 1900 h

  1. 1.1Evolution of FPGAs and programmable SoCs
  2. 1.2Logic blocks, LUTs and flip-flops
  3. 1.3DSP blocks and BRAM and URAM memories
  4. 1.4High-speed serial transceivers
  5. 1.5AMD Zynq UltraScale+ and Versal families
  6. 1.6Intel Agilex and Stratix families
  7. 1.7FPGA versus ASIC, GPU and CPU
  8. 1.8Design flow from RTL to bitstream
  9. 1.9Device selection criteria
  10. 1.10Case study: device selection for machine vision
  1. 2.1Abstraction levels and the synthesisable subset
  2. 2.2Combinational and sequential logic
  3. 2.3Finite state machines and encoding
  4. 2.4Datapath pipelining
  5. 2.5SystemVerilog types, packages and interfaces
  6. 2.6Parameterisable design with generics
  7. 2.7Clock and reset strategies
  8. 2.8Inference of memories and DSP blocks
  9. 2.9Style guides and code review
  10. 2.10Practical exercise: RTL design of a UART controller
  1. 3.1ARM processor subsystem in Zynq
  2. 3.2The AMBA AXI4 protocol and its channels
  3. 3.3AXI4-Lite and AXI4-Stream variants
  4. 3.4Interconnects, arbitration and quality of service
  5. 3.5Address maps and control registers
  6. 3.6Integration of IP cores in Vivado
  7. 3.7DDR4 and LPDDR4 memory controllers
  8. 3.8Cache coherency with ACP ports
  9. 3.9Interrupts from logic to processor
  10. 3.10Lab: custom AXI peripheral on Zynq
  1. 4.1Principles of high-level synthesis
  2. 4.2Loop pipelining and initiation interval
  3. 4.3Loop unrolling and parallelism
  4. 4.4Array partitioning into memories
  5. 4.5Generating AXI interfaces from C++
  6. 4.6Arbitrary-precision types
  7. 4.7Latency and resource estimation
  8. 4.8C/RTL co-simulation
  9. 4.9Limitations and good practice in HLS
  10. 4.10Workshop: image filtering accelerator with Vitis HLS
  1. 5.1Static timing analysis
  2. 5.2Clock constraints in XDC format
  3. 5.3Critical paths and negative slack
  4. 5.4Clock domain crossing
  5. 5.5Synchronisers and asynchronous FIFOs
  6. 5.6Timing exceptions: false paths and multicycle paths
  7. 5.7Placement, routing and congestion
  8. 5.8Floorplanning and Pblocks
  9. 5.9Implementation strategies for timing closure
  10. 5.10Practical exercise: timing closure of a 300 MHz design
  1. 6.1Verification plan and metrics
  2. 6.2SystemVerilog testbenches
  3. 6.3SystemVerilog assertions (SVA)
  4. 6.4Functional and code coverage
  5. 6.5UVM methodology: agents and sequences
  6. 6.6Formal property verification
  7. 6.7Fast simulation with Verilator
  8. 6.8Reference models in C and Python
  9. 6.9Automated regressions in continuous integration
  10. 6.10Lab: UVM environment for an AXI peripheral
  1. 7.1Partitioning functions between software and logic
  2. 7.2Profiling to identify acceleration candidates
  3. 7.3Linux drivers for peripherals in logic
  4. 7.4Bare-metal and RTOS applications on Zynq
  5. 7.5DMA transfers and shared memory
  6. 7.6Dynamic partial reconfiguration
  7. 7.7Vitis platforms and flows
  8. 7.8End-to-end performance measurement
  9. 7.9Joint hardware and software debugging
  10. 7.10Case study: acceleration of a vision algorithm
  1. 8.1Multi-gigabit transceiver architecture
  2. 8.2PCI Express in programmable logic
  3. 8.3Ethernet from 10 to 100 Gb/s
  4. 8.4JESD204B/C interface for converters
  5. 8.5High-bandwidth memory interfaces
  6. 8.6Signal integrity and eye diagrams
  7. 8.7Link equalisation and calibration
  8. 8.8Testing with IBERT and PRBS patterns
  9. 8.9Laboratory validation of interfaces
  10. 8.10Practical exercise: PCIe link between FPGA and host
  1. 9.1Static and dynamic power in FPGAs
  2. 9.2Power estimation with vendor tools
  3. 9.3Power reduction techniques
  4. 9.4Device thermal management
  5. 9.5Radiation effects and SEUs
  6. 9.6Triple modular redundancy and memory scrubbing
  7. 9.7ECC error detection and correction
  8. 9.8DO-254 requirements for complex hardware
  9. 9.9Functional safety to IEC 61508
  10. 9.10Workshop: power analysis and SEU mitigation
  1. 10.1Neural network inference on FPGAs
  2. 10.2Quantisation and low-precision arithmetic
  3. 10.3DPU processing units
  4. 10.4AI Engines in the Versal family
  5. 10.5Vitis AI compilers and flows
  6. 10.6Latency and throughput compared with GPUs
  7. 10.7Dataflow architectures
  8. 10.8Applications in vision and radar
  9. 10.9Memory optimisation in accelerators
  10. 10.10Lab: deploying a convolutional network with Vitis AI
  1. 11.1Integrated logic analysers (ILA)
  2. 11.2On-board debugging with JTAG
  3. 11.3Bitstream encryption and authentication
  4. 11.4Secure boot on programmable SoCs
  5. 11.5Physical and side-channel attacks
  6. 11.6IP protection to IEEE 1735
  7. 11.7Production testing and boundary scan
  8. 11.8Hardware version management
  9. 11.9Documentation for manufacturing
  10. 11.10Case study: debugging an intermittent fault with ILA
  1. 12.1System definition and requirements
  2. 12.2Hardware-software architecture of the SoC
  3. 12.3RTL design and high-level synthesis
  4. 12.4Integration of the processor subsystem
  5. 12.5Functional verification of the design
  6. 12.6Implementation and timing closure
  7. 12.7Performance and power evaluation
  8. 12.8Conclusions and future work
  9. 12.9Master's Thesis report
  10. 12.10Master's Thesis: defence before a panel
Methodology, software & labs

How you'll learn

Training is 100% online on the SEIUM campus, with downloadable material, recorded classes and an assigned technical tutor. There are no fixed timetables: you progress at your own pace within each intake, so the programme is compatible with work.

Each module combines theory, guided reading of the original standard and applied exercises. The working software is AMD Vivado, AMD Vitis, Intel Quartus Prime, Siemens Questa and Verilator, in free, academic or evaluation versions. Exercises are based on real procedures for RTL design and FPGA implementation, integration of processor and programmable logic in an SoC, and functional verification with UVM testbenches. Assessment is continuous per module, plus the final Master's Thesis.

Standards covered: AMBA AXI4, IEEE 1800 SystemVerilog, IEEE 1076 VHDL, IEEE 1149.1, RTCA DO-254, IEEE 1735, Accellera UVM 1.2 and IEC 61508.

Assigned technical tutor:every module ends with a deliverable that your tutor marks individually.
Standards-based learning:guided reading of AMBA AXI4, IEEE 1800 SystemVerilog and IEEE 1076 VHDL applied to real cases, not as a theoretical annex.
Industry software:AMD Vivado, AMD Vitis, Intel Quartus Prime, Siemens Questa and Verilator, in free, academic or evaluation versions.
Master's Thesis with defence:a complete SoC/FPGA system, from hardware-software architecture and RTL/HLS design to verification, timing closure and performance evaluation, defended before a panel.
Flexible format:100% online, no fixed timetables, compatible with full-time work.
Capstone project

Build it end to end

Your final project follows the real engineering workflow, step by step, reviewed by your tutor.

Custom AXI peripheral
Design an RTL peripheral and integrate it over AXI with the Zynq processor.
HLS accelerator
Build an image filtering accelerator with Vitis HLS and co-simulate it.
Timing closure
Constrain and close timing of a 300 MHz design, including clock domain crossings.
UVM verification
Build a UVM environment with assertions and coverage for the peripheral.
Master's Thesis
A complete, verified and timing-closed SoC/FPGA system, defended before a panel.
Career opportunities

Where this takes you

FPGA design engineerSoC architecture engineerHardware verification engineerHardware-software co-design engineerHardware accelerator engineerEmbedded systems engineer
Admissions & scholarships

Requirements

  • University degree in engineering, science or architecture, or equivalent demonstrable professional experience.
  • An internet connection and a computer able to run the programme software.
  • English sufficient to read technical standards.

Ready to start?

Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.

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FAQ

Frequently asked questions

The programme totals 1,900 hours over 12–14 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.

You work with AMD Vivado, AMD Vitis, Intel Quartus Prime, Siemens Questa and Verilator, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.

A SEIUM Institute diploma, awarded on passing the continuous assessment and the Master's Thesis. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.

Yes. Modules passed in a course or postgraduate diploma in the same area are recognised in the higher programme. Ask about the recognition policy when you enrol.

A university degree in engineering, science or architecture (or equivalent professional experience), a computer able to run the software and English sufficient to read technical standards.

Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.

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