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Master'sElectronics, Embedded Systems & Telecom Applications open

Master’s in Embedded, Firmware and Real-Time Engineering

Online master's programme of 1,900 hours in embedded systems, firmware and real-time engineering. 12 modules covering microcontroller architecture, embedded C and C++ to MISRA C:2012, drivers and peripherals, RTOS, timing analysis, software design, connectivity, power management, verification, functional safety to IEC 61508 and ISO 26262, and firmware cybersecurity, with an assigned technical tutor.

Duration1900 h
ModeOnline
LanguageEnglish
Start datesSet by the faculty
AwardSEIUM Institute diploma
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Learning outcomes

What you will be able to do

01

Design firmware architectures on modern microcontrollers.

02

Program in embedded C and C++ following secure coding standards.

03

Develop applications on real-time operating systems.

04

Integrate peripherals, communication buses and power management.

05

Analyse system response times and schedulability.

06

Verify firmware with automated testing and static analysis.

07

Apply functional safety and cybersecurity requirements to firmware.

Profile

Who it's for

  • Firmware engineers in automotive, aerospace or medical devices.
  • Embedded systems engineers.
  • Real-time software developers.
  • Functional safety engineers.
  • Embedded software verification engineers.
  • Embedded systems architects.
  • Engineering or science graduates looking to enter the automotive industry.
Standards & tools

What you'll work with

  • IEC 61508 (functional safety of E/E/PE systems)
  • ISO 26262 (functional safety of road vehicles)
  • MISRA C:2012 (C coding guidelines for critical systems)
  • RTCA DO-178C (software considerations in airborne systems)
  • IEC 62304 (medical device software)
  • AUTOSAR Classic Platform (automotive software architecture)
  • IEC 62443-4-2 (technical security requirements for IACS components)
  • CERT C Coding Standard (secure C coding)
  • STM32CubeIDE
  • FreeRTOS
  • Zephyr RTOS
  • Segger J-Link and Ozone
  • LDRA Testbed
Syllabus

12 modules · 1900 h

  1. 1.1Microcontrollers versus microprocessors
  2. 1.2ARM Cortex-M, Cortex-R and RISC-V cores
  3. 1.3Flash memory, SRAM and caches
  4. 1.4Memory map and peripherals
  5. 1.5Interrupts and the NVIC controller
  6. 1.6Clocks, PLLs and low-power modes
  7. 1.7Functional and non-functional requirements
  8. 1.8Microcontroller selection
  9. 1.9Toolchain and cross-compilers
  10. 1.10Case study: microcontroller selection for a product
  1. 2.1Data types and portability
  2. 2.2Pointers, volatile and register access
  3. 2.3Memory management without dynamic allocation
  4. 2.4Modern C++ in resource-constrained environments
  5. 2.5MISRA C:2012 guidelines
  6. 2.6The CERT C secure coding standard
  7. 2.7Optimisation and compiler control
  8. 2.8The linker and linker scripts
  9. 2.9Start-up code and the interrupt vector table
  10. 2.10Practical exercise: bare-metal firmware on STM32
  1. 3.1Hardware abstraction layer (HAL)
  2. 3.2GPIO, timers and PWM
  3. 3.3ADC and DAC converters
  4. 3.4DMA and efficient transfers
  5. 3.5UART, SPI and I²C buses
  6. 3.6CAN and CAN FD bus
  7. 3.7Embedded USB and Ethernet
  8. 3.8External flash memory management
  9. 3.9Designing reusable drivers
  10. 3.10Lab: SPI driver with DMA
  1. 4.1Hard and soft real-time concepts
  2. 4.2Tasks, priorities and the scheduler
  3. 4.3Semaphores, mutexes and queues
  4. 4.4Priority inversion and inheritance
  5. 4.5Software timers and ticks
  6. 4.6Memory management in an RTOS
  7. 4.7FreeRTOS: architecture and configuration
  8. 4.8Zephyr RTOS and its device model
  9. 4.9Comparison of commercial RTOSs
  10. 4.10Practical exercise: multitasking application with FreeRTOS
  1. 5.1Periodic and sporadic task models
  2. 5.2Fixed-priority and rate-monotonic scheduling
  3. 5.3Earliest deadline first (EDF) scheduling
  4. 5.4Response time analysis
  5. 5.5Worst-case execution time estimation
  6. 5.6Interrupt latency and jitter
  7. 5.7Tracing with Segger SystemView
  8. 5.8Timing measurement with an oscilloscope
  9. 5.9Designing for determinism
  10. 5.10Lab: schedulability analysis of a system
  1. 6.1Layered and event-driven architectures
  2. 6.2Hierarchical state machines
  3. 6.3Embedded design patterns
  4. 6.4Component-oriented design
  5. 6.5Modelling with UML and SysML
  6. 6.6Code generation from models
  7. 6.7Configuration and variant management
  8. 6.8Architecture documentation
  9. 6.9Design and code reviews
  10. 6.10Workshop: design with state machines
  1. 7.1Lightweight TCP/IP stacks such as lwIP
  2. 7.2Bluetooth Low Energy
  3. 7.3LoRaWAN and NB-IoT networks
  4. 7.4MQTT and CoAP protocols
  5. 7.5Modbus and industrial protocols
  6. 7.6Buffer and stream management
  7. 7.7Communication reliability
  8. 7.8Communication security with TLS
  9. 7.9Over-the-air firmware updates
  10. 7.10Practical exercise: IoT node with MQTT on Zephyr
  1. 8.1Low-power and wake-up modes
  2. 8.2Energy consumption profiling
  3. 8.3Design for batteries and energy harvesting
  4. 8.4Dynamic voltage and frequency scaling
  5. 8.5Clock and peripheral management
  6. 8.6Measurement with power analysers
  7. 8.7Duty cycle optimisation
  8. 8.8Fast start-up and data retention
  9. 8.9Wearable and portable device cases
  10. 8.10Lab: optimising the consumption of a sensor
  1. 9.1Debugging with JTAG and SWD
  2. 9.2Breakpoints and ETM traces
  3. 9.3Unit testing with Unity and CppUTest
  4. 9.4Test-driven development for embedded systems
  5. 9.5Hardware-in-the-loop testing of firmware
  6. 9.6Static code analysis
  7. 9.7MC/DC structural coverage
  8. 9.8Continuous integration for firmware
  9. 9.9Automated regression testing
  10. 9.10Practical exercise: continuous integration pipeline with tests
  1. 10.1IEC 61508 concepts
  2. 10.2SIL and ASIL levels
  3. 10.3Software safety life cycle
  4. 10.4ISO 26262 Part 6
  5. 10.5Diagnostic mechanisms and watchdog
  6. 10.6Partitioning and memory protection
  7. 10.7Qualification of development tools
  8. 10.8DO-178C and IEC 62304 requirements
  9. 10.9Evidence and the safety case
  10. 10.10Case study: safety analysis of a controller
  1. 11.1Threat modelling for devices
  2. 11.2Secure boot and chain of trust
  3. 11.3Secure key storage
  4. 11.4Secure elements and TrustZone
  5. 11.5Signed firmware updates
  6. 11.6Debug protection
  7. 11.7IEC 62443-4-2 requirements
  8. 11.8Vulnerability management
  9. 11.9The European Cyber Resilience Act
  10. 11.10Workshop: implementing secure boot
  1. 12.1Defining the embedded product
  2. 12.2Requirements specification
  3. 12.3Hardware and software architecture
  4. 12.4Firmware development
  5. 12.5RTOS integration
  6. 12.6Verification and timing analysis
  7. 12.7Safety assessment
  8. 12.8Conclusions and future work
  9. 12.9Master's Thesis report
  10. 12.10Master's Thesis: defence before a panel
Methodology, software & labs

How you'll learn

Training is 100% online on the SEIUM campus, with downloadable material, recorded classes and an assigned technical tutor. There are no fixed timetables: you progress at your own pace within each intake, so the programme is compatible with work.

Each module combines theory, guided reading of the original standard and applied exercises. The working software is STM32CubeIDE, FreeRTOS, Zephyr RTOS, Segger J-Link and Ozone, and LDRA Testbed, in free, academic or evaluation versions. Exercises are based on real procedures for developing firmware on ARM Cortex-M microcontrollers, real-time response analysis, and unit and integration testing on hardware. Assessment is continuous per module, plus the final Master's Thesis.

Standards covered: IEC 61508, ISO 26262, MISRA C:2012, RTCA DO-178C, IEC 62304, AUTOSAR Classic Platform, IEC 62443-4-2 and CERT C.

Assigned technical tutor:every module ends with a deliverable that your tutor marks individually.
Standards-based learning:guided reading of IEC 61508, ISO 26262 and MISRA C:2012 applied to real cases, not as a theoretical annex.
Industry software:STM32CubeIDE, FreeRTOS, Zephyr RTOS, Segger J-Link and Ozone, and LDRA Testbed, in free, academic or evaluation versions.
Master's Thesis with defence:a complete embedded product, from requirements and architecture to RTOS-based firmware, timing verification and safety assessment, defended before a panel.
Flexible format:100% online, no fixed timetables, compatible with full-time work.
Capstone project

Build it end to end

Your final project follows the real engineering workflow, step by step, reviewed by your tutor.

Bare-metal firmware
Write start-up code, linker script and drivers for an STM32 microcontroller.
Multitasking RTOS application
Build a FreeRTOS application with tasks, queues and mutexes.
Schedulability analysis
Analyse response times and worst-case timing of a real-time system and verify them with tracing.
CI pipeline with tests
Set up unit tests, static analysis and continuous integration for the firmware.
Master's Thesis
A complete embedded product with verified firmware and a safety assessment, defended before a panel.
Career opportunities

Where this takes you

Firmware engineerEmbedded systems engineerReal-time software developerFunctional safety engineerEmbedded software verification engineerEmbedded systems architect
Admissions & scholarships

Requirements

  • University degree in engineering, science or architecture, or equivalent demonstrable professional experience.
  • An internet connection and a computer able to run the programme software.
  • English sufficient to read technical standards.

Ready to start?

Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.

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FAQ

Frequently asked questions

The programme totals 1,900 hours over 12–14 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.

You work with STM32CubeIDE, FreeRTOS, Zephyr RTOS, Segger J-Link and Ozone, and LDRA Testbed, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.

A SEIUM Institute diploma, awarded on passing the continuous assessment and the Master's Thesis. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.

Yes. Modules passed in a course or postgraduate diploma in the same area are recognised in the higher programme. Ask about the recognition policy when you enrol.

A university degree in engineering, science or architecture (or equivalent professional experience), a computer able to run the software and English sufficient to read technical standards.

Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.

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