Apply now
Master'sData, AI, Simulation & Analytics Applications open

Master’s in Edge AI & TinyML Engineering

Online master's programme of 1,900 hours in edge AI and TinyML: 12 modules covering microcontrollers and embedded systems, efficient neural networks, model compression, frameworks and compilers, accelerators, embedded vision, audio and sensors, on-device learning, MLOps for TinyML and product regulation, with an assigned technical tutor.

Duration1900 h
ModeOnline
LanguageEnglish
Start datesSet by the faculty
AwardSEIUM Institute diploma
Enrol now View syllabus Ask an advisor
Virtual lab · try it before you enrol

Take the controls.

Run a real engineering trade-off from this field. Move the sliders, watch the model react in real time and beat the challenge.

SIM · LIVE ●
Learning outcomes

What you will be able to do

01

Select suitable embedded hardware for AI workloads.

02

Design efficient neural networks for microcontrollers.

03

Compress models through quantisation, pruning and distillation.

04

Deploy models with edge frameworks and compilers.

05

Develop on-device vision, audio and sensor applications.

06

Implement MLOps cycles and OTA model updates.

07

Ensure the regulatory compliance of products with embedded AI.

Profile

Who it's for

  • TinyML engineers fitting neural networks into kilobytes of memory.
  • Embedded AI engineers deploying inference on MCUs and NPUs.
  • Firmware developers adding machine learning to existing products.
  • Embedded vision engineers working with low-power cameras.
  • IoT device architects defining hardware, firmware and update strategies.
  • Model optimisation engineers specialising in quantisation and compilation.
  • Engineering or science graduates aiming to move into consumer electronics.
Standards & tools

What you'll work with

  • ETSI EN 303 645 (cybersecurity for consumer IoT devices)
  • Regulation (EU) 2024/2847 (Cyber Resilience Act) (cybersecurity requirements for products with digital elements)
  • Regulation (EU) 2024/1689 (AI Act) (European Artificial Intelligence Regulation)
  • Directive 2014/53/EU (radio equipment) (Radio Equipment Directive)
  • IEC 62443-4-2 (industrial cybersecurity: technical requirements for components)
  • Regulation (EU) 2024/1781 (ecodesign) (Ecodesign for Sustainable Products Regulation)
  • IEC 62368-1 (safety of audio/video, information and communication technology equipment)
  • TensorFlow Lite Micro
  • Edge Impulse
  • STM32Cube.AI
  • Apache TVM
  • Zephyr RTOS
Syllabus

12 modules · 1900 h

  1. 1.1Motivations: latency, privacy and energy
  2. 1.2The spectrum from the cloud to the microcontroller
  3. 1.3TinyML use cases
  4. 1.4Flash memory and RAM constraints
  5. 1.5The hardware and software ecosystem
  6. 1.6The MLPerf Tiny benchmark
  7. 1.7The economics of smart devices
  8. 1.8Sustainability and the footprint of edge AI
  9. 1.9Open research challenges
  10. 1.10Case study: feasibility analysis of a TinyML product
  1. 2.1ARM Cortex-M architecture
  2. 2.2DSP and Helium extensions
  3. 2.3RISC-V architecture and vector extensions
  4. 2.4Memory maps and linking
  5. 2.5Peripherals: ADC, I2S, SPI and I2C
  6. 2.6FreeRTOS and Zephyr operating systems
  7. 2.7Power management and sleep modes
  8. 2.8JTAG and SWD debugging tools
  9. 2.9On-board power measurement
  10. 2.10Lab: I2S audio acquisition in Zephyr
  1. 3.1The cost of MAC operations and parameters
  2. 3.2Depthwise separable convolutions
  3. 3.3MobileNet, EfficientNet and MCUNet
  4. 3.4Networks for audio: DS-CNN
  5. 3.5Lightweight recurrent networks
  6. 3.6Efficient attention for the edge
  7. 3.7Hardware-constrained architecture search
  8. 3.8Binary and ternary networks
  9. 3.9Neuromorphic spiking networks
  10. 3.10Practical: designing a DS-CNN for keyword spotting
  1. 4.18-bit integer quantisation
  2. 4.2Per-channel and symmetric quantisation
  3. 4.3Sub-8-bit quantisation
  4. 4.4Quantisation-aware training
  5. 4.5Magnitude-based and structured pruning
  6. 4.6Teacher-student distillation
  7. 4.7Low-rank factorisation
  8. 4.8Weight clustering
  9. 4.9Measuring the impact on accuracy
  10. 4.10Lab: compressing an image classifier
  1. 5.1TensorFlow Lite and LiteRT for microcontrollers
  2. 5.2PyTorch ExecuTorch
  3. 5.3ONNX Runtime for devices
  4. 5.4Apache TVM and microTVM
  5. 5.5STM32Cube.AI and vendor tools
  6. 5.6CMSIS-NN optimised kernels
  7. 5.7Tensor memory planning
  8. 5.8C code generation
  9. 5.9Performance comparison
  10. 5.10Practical: the same network with TFLite Micro and microTVM
  1. 6.1NPUs integrated into microcontrollers
  2. 6.2Arm Ethos-U NPU architecture
  3. 6.3Coral Edge TPU
  4. 6.4NVIDIA Jetson modules for the edge
  5. 6.5FPGA inference with hls4ml
  6. 6.6In-memory computing
  7. 6.7Neuromorphic processors and spiking computation
  8. 6.8Hardware-software co-simulation of accelerators
  9. 6.9Accelerator selection
  10. 6.10Case study: migrating a model to Ethos-U
  1. 7.1Low-power image sensors
  2. 7.2Image classification on MCUs
  3. 7.3Lightweight object detection
  4. 7.4Person and presence detection
  5. 7.5Segmentation at the edge
  6. 7.6Efficient image preprocessing
  7. 7.7Smart cameras with NPUs
  8. 7.8On-device visual privacy
  9. 7.9Evaluation in real-world conditions
  10. 7.10Workshop: person detector on a camera board
  1. 8.1Keyword spotting
  2. 8.2Acoustic event classification
  3. 8.3Real-time mel spectrograms
  4. 8.4Gesture recognition with an IMU
  5. 8.5Vibration monitoring
  6. 8.6On-device sensor fusion
  7. 8.7Embedded anomaly detection
  8. 8.8Sensors with integrated AI
  9. 8.9Always-on, low-power operation
  10. 8.10Lab: gesture recognition with an accelerometer
  1. 9.1Fine-tuning on microcontrollers
  2. 9.2Continual learning and catastrophic forgetting
  3. 9.3Few-shot learning
  4. 9.4Per-user personalisation
  5. 9.5Federated learning with devices
  6. 9.6Memory constraints for training
  7. 9.7Sparse backpropagation techniques
  8. 9.8Field evaluation
  9. 9.9Differential privacy at the edge
  10. 9.10Practical: personalising a gesture model
  1. 10.1The lifecycle of embedded models
  2. 10.2Collecting and labelling field data
  3. 10.3Development platforms such as Edge Impulse
  4. 10.4Continuous integration with hardware-in-the-loop testing
  5. 10.5OTA firmware updates
  6. 10.6Device fleet management
  7. 10.7Monitoring performance in the field
  8. 10.8Model and firmware versioning
  9. 10.9Traceability of deployed versions
  10. 10.10Workshop: OTA model update pipeline
  1. 11.1Secure boot and firmware security
  2. 11.2Protecting the intellectual property of the model
  3. 11.3Physical and side-channel attacks
  4. 11.4Device cybersecurity according to ETSI EN 303 645
  5. 11.5The Cyber Resilience Act
  6. 11.6The AI Act and AI-enabled devices
  7. 11.7The Radio Equipment Directive
  8. 11.8Ecodesign and energy consumption
  9. 11.9Certification and CE marking
  10. 11.10Case study: conformity file for a TinyML device
  1. 12.1Defining the product or use case
  2. 12.2Hardware and sensor selection
  3. 12.3Data collection
  4. 12.4Model design and training
  5. 12.5Compression and compilation
  6. 12.6Firmware integration
  7. 12.7Latency, memory and energy measurements
  8. 12.8Conclusions and product roadmap
  9. 12.9Thesis report
  10. 12.10Master's Thesis: defence before a panel
Methodology, software & labs

How you'll learn

100% online training on the SEIUM campus, with downloadable materials, recorded classes and an assigned technical tutor. There are no fixed timetables: you progress at your own pace within each intake, so the programme fits around your job.

Each module combines theory, guided reading of the original standard and applied exercises. The working software is TensorFlow Lite Micro, Edge Impulse, STM32Cube.AI, Apache TVM and Zephyr RTOS, in free, academic or evaluation versions. Real procedures are studied, such as keyword spotting on microcontrollers, person detection with low-power cameras and gesture recognition with inertial sensors. Assessment is continuous by module, plus the final Master's Thesis.

Standards covered: ETSI EN 303 645, Regulation (EU) 2024/2847 (Cyber Resilience Act), Regulation (EU) 2024/1689 (AI Act), Directive 2014/53/EU (radio equipment), IEC 62443-4-2, Regulation (EU) 2024/1781 (ecodesign), IEC 62368-1.

Assigned technical tutor:every module ends with a deliverable that your tutor marks individually.
Standards-based learning:guided reading of ETSI EN 303 645, the Cyber Resilience Act and the EU AI Act applied to real cases, not as a theoretical annex.
Industry software:TensorFlow Lite Micro, Edge Impulse, STM32Cube.AI, Apache TVM and Zephyr RTOS, in free, academic or evaluation versions.
Master's Thesis with defence:a TinyML product, from hardware selection and data collection to model compression, firmware integration and latency, memory and energy measurements, defended before a panel.
Flexible format:100% online, no fixed timetables, compatible with full-time work.
Capstone project

Build it end to end

Your final project follows the real engineering workflow, step by step, reviewed by your tutor.

Define the product
Define the use case and select the hardware and sensors.
Collect the data
Acquire field data with the board peripherals and label it.
Design and compress
Design an efficient network and compress it with quantisation and pruning.
Integrate into firmware
Compile the model and integrate it into the firmware with OTA updates.
Master's Thesis
Present latency, memory and energy measurements and the product roadmap, defended before a panel.
Career opportunities

Where this takes you

TinyML engineerEmbedded AI engineerFirmware developerEmbedded vision engineerIoT device architectModel optimisation engineer
Admissions & scholarships

Requirements

  • University degree in engineering, science or architecture, or equivalent demonstrable professional experience.
  • Internet connection and a computer capable of running the programme software.
  • English sufficient to read technical standards.

Ready to start?

Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.

Apply now Scholarships
FAQ

Frequently asked questions

The programme totals 1,900 hours over 12–14 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.

You work with TensorFlow Lite Micro, Edge Impulse, STM32Cube.AI, Apache TVM and Zephyr RTOS, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.

A SEIUM Institute diploma, awarded on passing the continuous assessment and the Master's Thesis. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.

Yes. Modules passed in a course or postgraduate diploma in the same area are recognised in the higher programme. Ask about the recognition policy when you enrol.

A university degree in engineering, science or architecture (or equivalent professional experience), a computer able to run the software and English sufficient to read technical standards.

Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.

Keep exploring

Related programmes

See all in Data, AI, Simulation & Analytics
Master's9,970 $

Master’s in Privacy, Federated and Graph Engineering

Online master's programme of 1,900 hours in privacy engineering, federated learning and graphs. 12 modules covering privacy in data systems, anonymisation, differential privacy, cryptography for learning,…

1900 hOnlineData, AI, Simulation & Analytics
Master's7,730 $

Master’s in HPC & GPU Engineering for Simulation and AI

Online master's programme of 1,900 hours in HPC and GPU engineering for simulation and AI. 12 modules covering GPU architecture, CUDA programming, performance portability, distributed computing,…

1900 hOnlineData, AI, Simulation & Analytics
Master's9,970 $

Master’s in Causality and Experimentation Engineering

Online master's programme of 1,900 hours in causality and experimentation: 12 modules covering causal frameworks, causal graphs, classical design of experiments, online A/B testing, complex experiments,…

1900 hOnlineData, AI, Simulation & Analytics
Master’s in Edge AI & TinyML EngineeringEnrol
Related programmes

More in Data, AI, Simulation & Analytics

Master’s in Graph ML Engineering for Networks and SystemsView programme →Master’s in Factory and Supply Chain Digital Twins Engineering — Discrete-Event Simulation, WIP/OEE and What-IfView programme →Master’s in Advanced Vision/Geomatics Engineering (Beyond Mobility)View programme →Master’s in Model Verification, Validation and UQ EngineeringView programme →Master’s in Traffic and Mobility Twins EngineeringView programme →Master’s in GeoAI & Dynamic Mapping EngineeringView programme →

All Data, AI, Simulation & Analytics programmes → · How to apply · Fees & financing · Scholarships

Scroll to Top
SEIUM – Institute of Advanced Engineering
Powered by  GDPR Cookie Compliance
Privacy Overview

This website uses cookies so that we can provide you with the best user experience possible. Cookie information is stored in your browser and performs functions such as recognising you when you return to our website and helping our team to understand which sections of the website you find most interesting and useful.