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Master'sAutonomous, ADAS & Software-Defined Vehicle Applications open

Master’s in Automotive RTOS and Hypervisors

Online master's programme of 1,900 hours in automotive RTOS and hypervisors. 12 modules covering real-time analysis, AUTOSAR Classic and Adaptive, embedded hypervisors, partitioning, secure boot, WCET and ISO 26262-6, with an assigned technical tutor.

Duration12–14 months
ModeOnline
LanguageEnglish
Start datesSet by the faculty
AwardSEIUM Institute diploma
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Learning outcomes

What you will be able to do

01

Explain the real-time requirements of automotive software.

02

Calculate response times and worst-case execution times.

03

Configure AUTOSAR Classic and OSEK operating systems.

04

Compare AUTOSAR Adaptive and POSIX environments for high-performance computing.

05

Design partitions with embedded hypervisors that guarantee freedom from interference.

06

Implement secure boot and update mechanisms.

07

Integrate several vehicle domains on a virtualised platform.

Profile

Who it's for

  • Automotive embedded software engineers.
  • Virtualised platform architects.
  • Real-time operating system engineers.
  • AUTOSAR integration engineers.
  • Timing analysis specialists.
  • Functional safety software engineers moving into platform software.
  • Engineering or science graduates seeking to enter vehicle manufacturers.
Standards & tools

What you'll work with

  • ISO 26262-6 (software for functional safety)
  • AUTOSAR Classic Platform (layered ECU software architecture)
  • ISO 17356 (OSEK/VDX)
  • AUTOSAR Adaptive Platform (service-oriented architecture for high-performance computers)
  • IEEE 1003.1 (POSIX)
  • MISRA C:2012 (C coding guidelines for critical systems)
  • Automotive SPICE (software process assessment)
  • Lauterbach TRACE32
  • Vector DaVinci Configurator
  • QNX Momentics
  • Xen Project
  • AbsInt aiT
Syllabus

12 modules

  1. 1.1Hard and soft requirements in the vehicle ECU
  2. 1.2Latency, jitter and determinism
  3. 1.3Periodic and sporadic task models
  4. 1.4Interrupts and their timing cost
  5. 1.5Critical sections and blocking
  6. 1.6Priority inversion and ceiling protocols
  7. 1.7Fixed and dynamic priority schedulers
  8. 1.8Utilisation-based schedulability analysis
  9. 1.9Bench measurement tools
  10. 1.10Workshop: timing characterisation of an ECU
  1. 2.1Worst-case response time
  2. 2.2Iterative calculation and convergence conditions
  3. 2.3Effect of interference from higher-priority tasks
  4. 2.4Offsets, release jitter and queues
  5. 2.5End-to-end event chains
  6. 2.6Buses and their contribution to delay
  7. 2.7Operating system overhead
  8. 2.8Design margins and CPU reserve
  9. 2.9Validation with real traces
  10. 2.10Case study: sensor-actuator chain
  1. 3.1Layered architecture of AUTOSAR Classic
  2. 3.2OSEK/VDX OS: tasks, events and alarms
  3. 3.3Scheduling schemes and schedule tables
  4. 3.4RTE and communication between components
  5. 3.5BSW: system, memory and communication services
  6. 3.6Configuration via ARXML
  7. 3.7Timing monitoring with WdgM and TimeE
  8. 3.8Memory protection on the MCU
  9. 3.9Generation and build flow
  10. 3.10Lab: integration of an SWC
  1. 4.1Service-oriented execution model
  2. 4.2ara::com and service discovery
  3. 4.3Execution management and machine states
  4. 4.4POSIX PSE51 and real-time constraints
  5. 4.5Scheduling in Linux: SCHED_FIFO and SCHED_DEADLINE
  6. 4.6PREEMPT_RT and its limits
  7. 4.7Containers and resource isolation
  8. 4.8Updating adaptive applications
  9. 4.9Classic-Adaptive interoperability
  10. 4.10Lab: adaptive service with deadlines
  1. 5.1Full virtualisation, paravirtualisation and containers
  2. 5.2Type 1 hypervisors in automotive
  3. 5.3Virtualisation extensions in ARMv8-A
  4. 5.4Static CPU and memory allocation
  5. 5.5Peripheral pass-through and SR-IOV
  6. 5.6GPU and accelerator virtualisation
  7. 5.7Guest boot and boot order
  8. 5.8Latency cost of virtualisation
  9. 5.9Comparison of market solutions
  10. 5.10Lab: deployment of two guests
  1. 6.1The concept of freedom from interference
  2. 6.2Spatial partitioning using MMU and MPU
  3. 6.3Temporal partitioning and CPU budgets
  4. 6.4Memory bandwidth control
  5. 6.5Contention in shared caches and buses
  6. 6.6Runtime resource monitoring
  7. 6.7Covert channels and their mitigation
  8. 6.8Partitioning evidence for certification
  9. 6.9Stress and saturation testing
  10. 6.10Workshop: measuring interference between partitions
  1. 7.1Chain of trust from boot
  2. 7.2Measured boot and storage of measurements
  3. 7.3Image signing and key management
  4. 7.4A/B updates and safe rollback
  5. 7.5OTA updates: campaigns and dependencies
  6. 7.6Updating the hypervisor versus the guests
  7. 7.7Runtime integrity and periodic checks
  8. 7.8Version management and software bill of materials
  9. 7.9Applicable UNECE R156 requirements
  10. 7.10Lab: complete update cycle
  1. 8.1Shared memory and message queues
  2. 8.2Virtio and paravirtualised drivers
  3. 8.3Virtualised buses: CAN, LIN and Ethernet
  4. 8.4SOME/IP between domains
  5. 8.5TSN Ethernet switching in the vehicle
  6. 8.6Priorities, shaping and bandwidth reservation
  7. 8.7End-to-end latency between guests
  8. 8.8Fault isolation in communication
  9. 8.9Diagnostics and distributed tracing
  10. 8.10Lab: deterministic channel between domains
  1. 9.1The safety element out of context concept
  2. 9.2Safety requirements allocated to the hypervisor
  3. 9.3ASIL decomposition and dependencies
  4. 9.4Dependent failure analysis
  5. 9.5Safety argument for partitioning
  6. 9.6Verification by analysis and by testing
  7. 9.7Structural coverage required by ASIL
  8. 9.8Tool management and qualification
  9. 9.9Safety case documentation
  10. 9.10Workshop: writing a partitioning argument
  1. 10.1Software versus hardware instrumentation
  2. 10.2ETM and ITM traces and debug probes
  3. 10.3WCET measurement: measurement-based, static and hybrid analysis
  4. 10.4Cache and branch prediction effects
  5. 10.5Representativeness of test scenarios
  6. 10.6Identification of peaks and outliers
  7. 10.7Trace visualisation and chain analysis
  8. 10.8Automating measurement in continuous integration
  9. 10.9Timing acceptance criteria
  10. 10.10Lab: WCET measurement campaign
  1. 11.1Domain and zonal computer architecture
  2. 11.2Coexistence of cockpit, ADAS and gateway
  3. 11.3Mixed-criticality requirements
  4. 11.4Power management and sleep states
  5. 11.5Fast start-up of critical functions
  6. 11.6Screen and audio sharing
  7. 11.7Unified diagnostics and UDS over IP
  8. 11.8Log and telemetry management
  9. 11.9Integration testing on the bench and in the vehicle
  10. 11.10Case study: integration of three domains
  1. 12.1Definition of requirements and timing constraints
  2. 12.2Choice of hypervisor and justification
  3. 12.3Partitioning design and budgets
  4. 12.4Implementation of communication between guests
  5. 12.5Integration of a function with safety requirements
  6. 12.6Measurement campaign and analysis of results
  7. 12.7Evidence for the safety case
  8. 12.8Update and cybersecurity plan
  9. 12.9Technical report and defence
  10. 12.10Master's Thesis: final review with the tutor
Methodology, software & labs

How you'll learn

A 100% online programme on the SEIUM campus, with downloadable materials, recorded classes and an assigned technical tutor. There are no fixed timetables: you progress at your own pace within each intake, so it fits around your job.

Each module combines theory, guided reading of the original standard and applied exercises. The working software is Lauterbach TRACE32, Vector DaVinci Configurator, QNX Momentics, Xen Project and AbsInt aiT, in free, academic or evaluation versions. Testing is studied through real procedures for response-time and WCET analysis, integration on evaluation boards and freedom-from-interference testing. Assessment is continuous by module, plus the final Master's Thesis.

Standards covered: ISO 26262-6, AUTOSAR Classic Platform, ISO 17356 (OSEK/VDX), AUTOSAR Adaptive Platform, IEEE 1003.1 (POSIX), MISRA C:2012 and Automotive SPICE.

Assigned technical tutor:every module ends with a deliverable that your tutor marks individually.
Standards-based learning:guided reading of ISO 26262-6, AUTOSAR Classic Platform and ISO 17356 (OSEK/VDX) applied to real cases, not as a theoretical annex.
Industry software:Lauterbach TRACE32, Vector DaVinci Configurator, QNX Momentics, Xen Project and AbsInt aiT, in free, academic or evaluation versions.
Master's Thesis with defence:the design, integration and timing validation of a virtualised automotive platform, defended before a panel.
Flexible format:100% online, no fixed timetables, compatible with full-time work.
Capstone project

Build it end to end

Your final project follows the real engineering workflow, step by step, reviewed by your tutor.

ECU timing characterisation
Measure and characterise the timing behaviour of an ECU on the bench.
AUTOSAR SWC integration
Integrate a software component into an AUTOSAR Classic stack configured via ARXML.
Two-guest hypervisor deployment
Deploy two guests on an embedded hypervisor and measure interference between partitions.
WCET measurement campaign
Run a WCET measurement campaign and assess the results against timing acceptance criteria.
Master's Thesis
Design and validate a virtualised platform integrating several vehicle domains, defended before a panel.
Career opportunities

Where this takes you

Automotive embedded software engineerVirtualised platform architectReal-time operating systems engineerAUTOSAR integration engineerTiming analysis specialistFunctional safety software engineer
Admissions & scholarships

Requirements

  • University degree in engineering, science or architecture, or equivalent demonstrable professional experience.
  • Internet connection and a computer capable of running the programme's software.
  • English sufficient to read technical standards.

Ready to start?

Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.

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FAQ

Frequently asked questions

The programme totals 1,900 hours over 12–14 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.

You will work with Lauterbach TRACE32, Vector DaVinci Configurator, QNX Momentics, Xen Project and AbsInt aiT. Free, academic or evaluation versions are used, and your tutor indicates the free alternative where one exists.

A SEIUM Institute diploma, awarded on passing the continuous assessment and the Master's Thesis. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.

Yes. Modules passed in a course or postgraduate diploma in the same area are recognised in the higher programme. Ask about the recognition policy when you enrol.

A university degree in engineering, science or architecture, or equivalent professional experience; a computer able to run the programme's software; and English sufficient to read technical standards.

Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.

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