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Postgraduate DiplomaAerospace, UAM, Drones & Space Applications open

Diploma in Aeronautical Hardware Design and Verification (DO-254)

Online postgraduate diploma of 800 hours in airborne electronic hardware design and verification (DO-254): 8 modules covering the hardware life cycle, hardware planning, requirements and conceptual design, detailed design and implementation, functional verification, level A and B objectives, and configuration, quality and certification, with an assigned technical tutor.

Duration6–8 months
ModeOnline
LanguageEnglish
Start datesSet by the faculty
AwardSEIUM Institute diploma
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Learning outcomes

What you will be able to do

01

Understand the hardware life cycle according to DO-254 and AMC 20-152A.

02

Prepare hardware plans and design standards.

03

Capture verifiable and traceable hardware requirements.

04

Implement HDL designs following safe coding rules.

05

Verify designs through simulation and testing on the target hardware.

06

Apply the additional objectives for levels A and B.

07

Prepare the certification evidence for airborne electronic hardware.

Profile

Who it's for

  • Airborne hardware engineers.
  • FPGA verification engineers.
  • FPGA designers moving into certified avionics.
  • Hardware certification engineers.
  • Process assurance managers.
  • Avionics electronics engineers.
  • Engineering or science graduates looking to enter avionics.
Standards & tools

What you'll work with

  • RTCA DO-254 (design assurance guidance for airborne electronic hardware)
  • AMC 20-152A (EASA acceptable means of compliance for airborne electronic hardware)
  • SAE ARP4754B (development of civil aircraft and systems)
  • RTCA DO-160G (environmental conditions and test procedures for airborne equipment)
  • SAE ARP4761A (safety assessment process for civil aircraft and systems)
  • IEEE 1076 (VHDL) (VHDL language reference)
  • IEEE 1800 (SystemVerilog) (SystemVerilog language reference)
  • Siemens Questa
  • AMD Vivado
  • Microchip Libero SoC
  • Jama Connect
Syllabus

8 modules

  1. 1.1Scope of DO-254 and AMC 20-152A
  2. 1.2Simple versus complex hardware
  3. 1.3Assurance levels A to E
  4. 1.4Planning and design processes
  5. 1.5Supporting processes
  6. 1.6Stages of involvement
  7. 1.7Commercial off-the-shelf (COTS) components
  8. 1.8Relationship with systems and safety
  9. 1.9Life-cycle data
  10. 1.10Workshop: classifying the components of a unit
  1. 2.1Plan for Hardware Aspects of Certification (PHAC)
  2. 2.2Design, verification and configuration plans
  3. 2.3Requirements and design standards
  4. 2.4HDL coding standards
  5. 2.5Assessment of design tools
  6. 2.6Assessment of verification tools
  7. 2.7Use of IP cores
  8. 2.8Previously developed hardware
  9. 2.9Supplier oversight
  10. 2.10Practical: preparing a PHAC
  1. 3.1Capturing hardware requirements
  2. 3.2Derived requirements
  3. 3.3Verifiability criteria
  4. 3.4Conceptual design
  5. 3.5FPGA and board architecture
  6. 3.6Hardware-level safety analysis
  7. 3.7Architectural mitigation
  8. 3.8Requirements traceability
  9. 3.9Requirements reviews
  10. 3.10Workshop: requirements for an actuator controller
  1. 4.1Coding in VHDL and Verilog
  2. 4.2Coding rules and linting
  3. 4.3Clock domain crossings
  4. 4.4Synthesis and place and route
  5. 4.5Static timing analysis
  6. 4.6Board design and component selection
  7. 4.7Manufacturing and production
  8. 4.8Production testing
  9. 4.9Hardware configuration data
  10. 4.10Lab: CDC analysis of a design
  1. 5.1Reviews and analyses
  2. 5.2Requirements-based simulation
  3. 5.3Self-checking testbenches
  4. 5.4Requirements coverage
  5. 5.5HDL code coverage
  6. 5.6Testing on the target hardware
  7. 5.7Robustness cases
  8. 5.8Verification independence
  9. 5.9Verification reports
  10. 5.10Practical: SystemVerilog testbench
  1. 6.1Functional failure path analysis
  2. 6.2Elemental analysis
  3. 6.3Architectures with monitoring
  4. 6.4Diversity and redundancy
  5. 6.5Formal verification
  6. 6.6Component errata
  7. 6.7SEU effects in FPGAs
  8. 6.8Multicore processors and AMC 20-193
  9. 6.9Complex COTS hardware
  10. 6.10Case study: FFPA of an FPGA
  1. 7.1Hardware configuration management
  2. 7.2Process assurance
  3. 7.3Problem reports
  4. 7.4Hardware Accomplishment Summary (HAS)
  5. 7.5Common audit findings
  6. 7.6Obsolescence and changes
  7. 7.7Series production
  8. 7.8In-service hardware
  9. 7.9Preparing SOI reviews
  10. 7.10Case study: SOI#2 audit
  1. 8.1Function and assurance level
  2. 8.2Project PHAC
  3. 8.3Requirements and traceability
  4. 8.4HDL design
  5. 8.5Verification and coverage
  6. 8.6Analysis for level A/B
  7. 8.7Accomplishment summary
  8. 8.8Conclusions
  9. 8.9Report and presentation
  10. 8.10Final project: final review with the tutor
Methodology, software & labs

How you'll learn

Training is 100% online on the SEIUM campus, with downloadable material, recorded classes and an assigned technical tutor. There are no fixed timetables: you progress at your own pace within each intake, so the programme fits around your job.

Each module combines theory, guided reading of the original standards and applied exercises. The working software is Siemens Questa, AMD Vivado, Microchip Libero SoC and Jama Connect, in free, academic or evaluation versions. Real procedures are studied: simulation of requirements-based testbenches, reviews of hardware plans and life-cycle data, and functional failure path analysis in FPGAs. Assessment is continuous by module, plus the final project.

Standards covered: RTCA DO-254, AMC 20-152A, SAE ARP4754B, RTCA DO-160G, SAE ARP4761A, IEEE 1076 (VHDL), IEEE 1800 (SystemVerilog).

Assigned technical tutor:every module ends with a deliverable that your tutor marks individually.
Standards-based learning:guided reading of RTCA DO-254, AMC 20-152A and SAE ARP4754B applied to real cases, not as a theoretical annex.
Industry software:Siemens Questa, AMD Vivado, Microchip Libero SoC and Jama Connect, in free, academic or evaluation versions.
Final project:An airborne hardware project, from PHAC and traceable requirements to HDL design, verification, coverage and accomplishment summary, reviewed by your tutor.
Flexible format:100% online, no fixed timetables, compatible with full-time work.
Capstone project

Build it end to end

Your final project follows the real engineering workflow, step by step, reviewed by your tutor.

Function and PHAC
Define the function, assign the assurance level and write the project PHAC.
Requirements and traceability
Capture verifiable hardware requirements with full traceability.
HDL design
Implement the HDL design following the coding standards.
Verification and coverage
Verify the design, measure coverage and complete the level A/B analyses.
Final project
A documented airborne hardware project with its accomplishment summary, reviewed by your tutor.
Career opportunities

Where this takes you

Airborne hardware engineerFPGA verification engineerFPGA designerHardware certification engineerProcess assurance managerAvionics electronics engineer
Admissions & scholarships

Requirements

  • Prior technical training or professional experience in the sector. No university degree is required.
  • An internet connection and a computer capable of running the programme software.
  • English sufficient to read technical standards.

Ready to start?

Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.

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FAQ

Frequently asked questions

The programme totals 800 hours over 6–8 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.

You work with Siemens Questa, AMD Vivado, Microchip Libero SoC and Jama Connect, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.

A SEIUM Institute diploma, awarded on passing the continuous assessment and the final project. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.

Yes. Modules passed are recognised in a higher programme in the same area (postgraduate diploma or master's). Ask about the recognition policy when you enrol.

Prior technical training or professional experience in the sector (no university degree required), a computer able to run the software, and English sufficient to read technical standards.

Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.

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