Diploma in SI/PI for DDR/SerDes and Current Return
Online postgraduate diploma of 800 hours in SI/PI for DDR/SerDes and current return. 8 modules covering high-speed signal integrity, return currents and planes, power integrity, DDR memory interfaces, multigigabit SerDes links, packages and transitions and SI/PI signoff with JEDEC JESD79-5 (DDR5), JESD209-5 (LPDDR5) and PCI Express 5.0, with an assigned technical tutor.
Take the controls.
Run a real engineering trade-off from this field. Move the sliders, watch the model react in real time and beat the challenge.
What you will be able to do
Analyse interconnects as transmission lines and channels.
Ensure low-inductance current return paths.
Design power distribution networks to a target impedance.
Simulate and optimise DDR memory interfaces.
Evaluate SerDes links with equalisation and COM metrics.
Model packages, connectors and via transitions.
Carry out joint signal and power integrity signoff.
Who it's for
- Signal integrity engineers working on DDR and SerDes channels.
- Power integrity engineers designing PDNs and decoupling.
- High-speed PCB designers who need to understand the physics behind the rules.
- Hardware engineers responsible for boards with fast memory and links.
- Package engineers modelling BGAs and transitions.
- Interface validation engineers correlating simulation with measurement.
- Engineering or science graduates looking to enter the semiconductor sector.
What you'll work with
- JEDEC JESD79-5 (DDR5) (DDR5 SDRAM standard)
- JEDEC JESD209-5 (LPDDR5) (low-power DDR5 standard)
- PCI Express Base Specification 5.0 (PCIe Gen5 interface)
- IBIS 7.2 (IBIS Open Forum) (I/O buffer behavioural models)
- IEEE 802.3-2022 (Ethernet, including the COM channel metric)
- JEDEC JESD79-4 (DDR4) (DDR4 SDRAM standard)
- IPC-2141A (controlled impedance circuit board design)
- Ansys SIwave
- Keysight ADS
- Cadence Sigrity
- Siemens HyperLynx
- Ansys HFSS
8 modules
1.1Transmission lines and characteristic impedance1.2Reflections and matching1.3Dielectric and conductor losses1.4NEXT and FEXT crosstalk1.5Interconnects as channels1.6S-parameters and their interpretation1.7Time domain versus frequency domain1.8IBIS and IBIS-AMI models1.9Effects of vias and discontinuities1.10Lab: channel simulation in ADS
2.1Lowest-inductance return path2.2Reference plane changes and stitching vias2.3Voids and splits in planes2.4Return in differential pairs2.5Coupling to power planes2.6Common mode and radiation2.7Stitching capacitors between planes2.8Connectors and current return2.9Visualisation of current density2.10Practical exercise: return analysis with a layer change
3.1Power distribution network (PDN)3.2Target impedance and its calculation3.3Decoupling capacitors and resonances3.4Mounting and via inductance3.5Power planes and cavities3.6DC drop and IR drop3.7Simultaneous switching noise3.8PDN interaction between package and die3.9PDN impedance measurement3.10Workshop: decoupling design with SIwave
4.1DDR4, DDR5 and LPDDR5 architecture4.2Fly-by and point-to-point topologies4.3ODT termination and ZQ calibration4.4Write levelling and read training4.5Timing budget and margin4.6DFE equalisation in DDR54.7Length and skew rules4.8DDR channel simulation4.9Eye diagram and masks4.10Lab: simulation of a DDR4 bus with IBIS
5.1SerDes architecture and encoding5.2NRZ versus PAM45.3CTLE, FFE and DFE equalisation5.4Insertion loss and channel budget5.5COM metric according to IEEE 802.35.6PCIe Gen5 and Gen65.7Statistical and bit-by-bit simulation5.8Jitter, BER and bathtub curves5.9Via design and back-drilling5.10Practical exercise: COM analysis of a 56 Gb/s channel
6.1Modelling BGA packages6.2Pin breakout and fan-out6.3Optimised via transitions6.4High-speed connector models6.5Cables and backplanes6.63D simulation with HFSS6.7Concatenation of channel models6.8Causality and passivity of models6.9Correlating models with VNA measurements6.10Case study: optimising a BGA-to-via transition
7.1SI and PI co-simulation7.2Power noise induced on signals7.3Jitter due to PDN noise7.4Coupled thermal-electrical analysis7.5Board signoff flow7.6Design rules derived from simulation7.7Layout review with automated tools7.8Documentation of margins7.9Design risk management7.10Case study: SI/PI signoff of a board with DDR5
8.1Definition of interfaces and requirements8.2Stackup and reference planes8.3Return path analysis8.4PDN and decoupling design8.5DDR interface simulation8.6SerDes link simulation8.7Signoff and margins8.8Layout recommendations8.9Report and presentation8.10Final project: final review with the tutor
How you'll learn
100% online training on the SEIUM campus, with downloadable material, recorded classes and an assigned technical tutor. No fixed timetables: you progress at your own pace within the intake, so it can be combined with work.
Each module combines theory, guided reading of the original standard and applied exercises. The working software is Ansys SIwave, Keysight ADS, Cadence Sigrity, Siemens HyperLynx and Ansys HFSS, in free, academic or evaluation versions. Testing is studied on real procedures: channel simulation with S-parameters, PDN impedance analysis and review of return paths in layout. Assessment is continuous by module plus the final project.
Standards covered: JEDEC JESD79-5 (DDR5), JEDEC JESD209-5 (LPDDR5), PCI Express Base Specification 5.0, IBIS 7.2 (IBIS Open Forum), IEEE 802.3-2022, JEDEC JESD79-4 (DDR4), IPC-2141A.
Build it end to end
Your final project follows the real engineering workflow, step by step, reviewed by your tutor.
Where this takes you
Requirements
- Prior technical training or professional experience in the sector. No university degree is required.
- Internet connection and a computer able to run the programme software.
- English sufficient to read technical standards.
Ready to start?
Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.
Frequently asked questions
The programme totals 800 hours over 6–8 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.
You work with Ansys SIwave, Keysight ADS, Cadence Sigrity, Siemens HyperLynx and Ansys HFSS, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.
A SEIUM Institute diploma, awarded on passing the continuous assessment and the final project. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.
Yes. Modules passed are recognised in a higher programme in the same area (postgraduate diploma or master's). Ask about the recognition policy when you enrol.
Prior technical training or professional experience in the sector (no university degree required), a computer able to run the software and English sufficient to read technical standards.
Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.
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